82544EI Datasheet, PDF (12/52 Pages) Intel Corporation – Gigabit Ethernet Controller

82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
3.2.1
PCI Address, Data and Control Signals
Signal Name
AD[63:0]
CBE[7:0]#
PAR
PAR64
FRAME#
IRDY#
Type
TS
TS
TS
TS
STS
STS
Name and Function
Address and Data. Address and Data are multiplexed on the same PCI
pins. A bus transaction consists of an address phase followed by one or
more data phases.
The address phase is the clock cycle in which FRAME# is asserted. During
the address phase AD[63:0] contain a physical address (64 bits). For I/O,
this is a byte address; for configuration and memory, it is a DWORD
address. The 82544EI device uses little endian byte ordering.
During data phases AD[7:0] contain the least significant byte (LSB) and
AD[63:56] contain the most significant byte (MSB).
The 82544EI controller may be optionally connected to a 32-bit PCI Local
Bus. On a 32-bit bus, AD[63:32] and other signals corresponding to the
high order byte lanes do not participate in the bus cycle.
Bus Command and Byte Enables. Bus Command and Byte Enables are
multiplexed on the same PCI pins.
During the address phase of a transaction, CBE#[7:0] define the bus
command. During the data phase CBE#[7:0] are used as Byte Enables.
The Byte Enables are valid for the entire data phase and determine which
byte lanes carry meaningful data.
CBE#[0] applies to byte 0 (LSB) and CBE#[7] applies to byte 7 (MSB).
Parity. Parity issued to implement Even Parity across AD[31:0] and
CBE#[3:0]. PAR is stable and valid one clock after the address phase. For
data phases, PAR is stable and valid one clock after either IRDY# is
asserted on a write transaction or TRDY# is asserted after a read
transaction. Once PAR is valid, it remains valid until one clock after the
completion of the current data phase.
When the 82544EI controller is a bus master, it drives PAR for address and
write data phases. As a slave, it drives PAR for read data phases.
Parity 64. Parity issued to implement Even Parity across AD[63:32] and
CBE#[7:4]. PAR64 is stable and valid one clock after the address phase.
For data phases, PAR is stable and valid one clock after either IRDY# is
asserted on a write transaction or TRDY# is asserted after a read
transaction. Once PAR is valid, it remains valid until one clock after the
completion of the current data phase.
When the 82544EI controller is a bus master, it drives PAR64 for address
and write data phases. As a slave, it drives PAR64 for read data phases.
FRAME. FRAME# is driven by the 82544EI device to indicate the
beginning and duration of an access. FRAME# is asserted to indicate the
beginning of a bus transaction.
While FRAME# is asserted, data transfers continue. When FRAME# is
asserted, the transaction is in the final data phase.
Initiator Ready. IRDY# indicates the ability of the 82544EI controller (as a
bus master device) to complete the current data phase of the transaction.
IRDY# is used in conjunction with TRDY#.
A data phase is completed on any clock in which both IRDY# and TRDY#
are sampled asserted.
During a write, IRDY# indicates that valid data is present on AD[63:0].
During a read, it indicates the master is ready to accept data. Wait cycles
are inserted until both IRDY# and TRDY# are asserted together. The
82544EI controller drives IRDY# when acting as a master and samples it
when acting as a slave.
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Datasheet