82544EI Datasheet, PDF (27/52 Pages) Intel Corporation – Gigabit Ethernet Controller

82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
4.5
Targeted Timing Specifications
Note: Timing specifications are preliminary and subject to change.
4.5.1
PCI/PCI-X Bus Interface
4.5.1.1 PCI/PCI-X Bus Interface Clock
Table 12. PCI/PCI-X Bus Interface Clock Parameters
Symbol
Parameter^a
PCI-X
133 MHz
Min Max
PCI-X
66 MHz
Min Max
PCI
66 MHz
Min Max
PCI
33 MHz
Min Max
Units
Notes
T_CYC
CLK Cycle Time 7.5 20 15 20 15 30 30
∞
ns
T_H
CLK High Time
3
6
6
11
ns
T_L
CLK Low Time
3
6
6
11
ns
CLK Slew Rate
1.5
4
1.5
4
1.5
4
1
4 V/ns a
RST# Slew Rate^b 50
50
50
50
mV/
b
ns
a. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum
peak-to-peak portion of the clock waveform as shown.
b. The minimum RST# slew rate applies only to the rising (de-assertion) edge of the reset signal, and ensures that system
noise cannot render an otherwise monotonic signal to appear to bounce in the switching range.
Figure 3. PCI/PCI-X Clock Timing
3.3 V Clock
0.5 Vcc
0.4 Vcc
0.3 Vcc
Tcyc
Th
0.6 Vcc
0.2 Vcc
Tl
0.4 Vcc p-to-p
(minimum)
Datasheet
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