82544EI Datasheet, PDF (18/52 Pages) Intel Corporation – Gigabit Ethernet Controller

82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
Signal Name
ABV_HI
BLW_LO
SDP[7:6]
SDP[4:0]
TEST0
TEST1
GMII_TEST[1:0]
COL_TEST
CRS_TEST
Type
O
O
TS
Name and Function
Above High Threshold. Output indicating the RX FIFO fullness is
above the programmed high threshold.
Below Low Threshold. Output indicating the RX FIFO fullness is
below the programmed low threshold.
S/W Defined Pins. These pins are reserved pins which are software
programmable with respect to input/output capability. These default
to inputs upon power up but may have their direction and output
values defined in the EEPROM. The upper four bits may be mapped
to the General Purpose Interrupt bits when configured as inputs.
SPECIAL NOTE: SDP5 is intentionally missing from the group of
software-defined pins.
I
Factory Test Pin. Connect this ball to ground through a pulldown
resistor.
Factory Test Pin. Attach an external pullup resistor to the pin to
ensure the test mode is disabled. Use a common value resistor such
as 1 KΩ (the value is not critical). Alternatively, the pin may be
connected directory to the 3.3V supply.
I
GMII Test Mode Pins. For normal operation, the test pins are
connected to ground through a common pulldown resistor. For PHY
Unfiltered Jitter Test, drive both pins high.
O
Collision Test Pin. For normal operation, these pins are connected
to ground through a pulldown resistor. During GMII test mode it is
driving as an output.
O
Carrier Sense Test Pin. For normal operation, this pin is connected
to ground through a pulldown resistor. It is driven as an output during
GMII test mode.
14
Datasheet