82544EI Datasheet, PDF (15/52 Pages) Intel Corporation – Gigabit Ethernet Controller

82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
3.2.6
3.2.7
3.3
Power Management Signals
Signal Name
LAN_PWR_GOOD
PME#
APM_WAKEUP
AUX_PWR
PWR_STATE[1:0]
Type
I
OD
O
I
O
Name and Function
Power Good (Power-On Reset). The LAN_PWR_GOOD signal
indicates that good power is available for 82544EI device. When the
signal is zero, the 82544EI controller will hold the entire chip in reset state
and float all PCI signals.
Power Management Event. The 82544EI device will drive this signal to
zero when it receives a wakeup event and either the PME_En bit in the
Power Management Control / Status Register is 1 or the Advanced Power
Management Enable (APME) bit of the Wake Up Control Register (WUC)
is 1.
Advance Power Management Wakeup. When APM Wakeup is enabled
in the 82544EI controller and the 82544EI controller receives a Magic
Packet* it will set this signal to a logic 1 for 50 ms.
Auxiliary Power Available. If AUX_PWR equals 1, it indicates that
Auxiliary Power is available and the 82544EI device should support D3_cold
power state.
Power State. The bits are set in the following power states:
00b = D0u, D1, or D3 state with wakeup disabled
• No PHY operation is required
01b = D0u, D1, or D3 state with wakeup enabled
• PHY operation is required in this state, although it may be at low
speed.
11b = D0 active state
• Full speed PHY operation is required.
The resulting meaning of the bits is as follows:
• Bit 1: asserted when normal (full power/speed) operation is required.
• Bit 0: asserted when link is required.
The polarity of bit 0 and 1 may be individually inverted by setting the IPS0
and IPS1 bits in the Extended Device Control Register (CTRL_EXT),
respectively.
Impedance Compensation Signals
Signal Name
ZN_COMP
ZP_COMP
Type
I/O
I/O
Name and Function
N Device Impedance Compensation. Connect to an external precision
resistor (to VDD) that is indicative of the PCI/PCI-X trace load. This cell is
used to dynamically determine the drive strength required on the N-channel
transistors in the PCI/PCI-X IO cells.
P Device Impedance Compensation. Connect to an external precision
resistor (to VSS) that is indicative of the PCI/PCI-X trace load. This cell is
used to dynamically determine the drive strength required on the P-channel
transistors in the PCI/PCI-X IO cells.
Ten-Bit Interface (TBI) Signals
The TBI is a MAC interface that can connect to an external Serializer/Deserializer (SERDES)
device for fiber-based designs. When the 82544EI controller is not in TBI mode, the TBI signals
are in a high-impedance state.
Datasheet
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