82544EI Datasheet, PDF (10/52 Pages) Intel Corporation – Gigabit Ethernet Controller

82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
• Implements a total of 64 KB of configurable receive and transmit data FIFOs:
— default allocation is 48 KB for Receive data FIFO and 16 KB for transmit data FIFO
• Descriptor ring management hardware for transmit and receive:
— optimized descriptor fetching and write-back mechanisms for efficient system memory
and PCI bandwidth usage
• Provides a mechanism for reducing the number of interrupts generated by receive and transmit
operations
• Supports reception and transmission of packets with length up to 16 KB
2.5
Additional Device Features
• Provides seven general-purpose user mode pins
• Supports little-endian byte ordering for both 32- and 64-bit systems
• Supports big-endian byte ordering for 64-bit systems
• Provides loopback capabilities
• Provides boundary scan through IEEE 1149.1 (JTAG) Test Access Port
2.6
Technology Features
• Implemented in 0.18µ process
• Packaged in 416 PBGA package (27 mm x 27 mm)
• Implemented as low power CMOS device
6
Datasheet