80960KA Datasheet, PDF (11/43 Pages) Intel Corporation – EMBEDDED 32-BIT MICROPROCESSOR

80960KA
Table 3. 80960KA Pin Description: L-Bus Signals (Sheet 1 of 2)
NAME
TYPE
DESCRIPTION
CLK2
I
SYSTEM CLOCK provides the fundamental timing for 80960KA systems. It is divided
by two inside the 80960KA to generate the internal processor clock.
LAD31:0
I/O LOCAL ADDRESS / DATA BUS carries 32-bit physical addresses and data to and
T.S. from memory. During an address (Ta) cycle, bits 2-31 contain a physical word
address (bits 0-1 indicate SIZE; see below). During a data (T_d) cycle, bits 0-31
contain read or write data. These pins float to a high impedance state when not
active.
Bits 0-1 comprise SIZE during a T_a cycle. SIZE specifies burst transfer size in words.
LAD1 LAD0
0
0
1 Word
0
1
2 Words
1
0
3 Words
1
1
4 Words
ALE
O ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE is
T.S. ^{asserted during a T}a ^{cycle and deasserted before the beginning of the T}d ^{state. It is}
active LOW and floats to a high impedance state during a hold cycle (T_h).
ADS
O
ADDRESS/DATA STATUS indicates an address state. ADS is asserted every T_a
O.D. state and deasserted during the following T_d state. For a burst transaction, ADS is
asserted again every T_d state where READY was asserted in the previous cycle.
W/R
O WRITE/READ specifies, during a T_a cycle, whether the operation is a write or read. It
O.D. is latched on-chip and remains valid during T_d cycles.
DT/R
O DATA TRANSMIT / RECEIVE indicates the direction of data transfer to and from the
O.D. ^{L-Bus. It is low during T}a ^{and T}d ^{cycles for a read or interrupt acknowledgment; it is}
high during T_a and T_d cycles for a write. DT/R never changes state when DEN is
asserted.
READY
I
READY indicates that data on LAD lines can be sampled or removed. If READY is not
asserted during a T_d cycle, the T_d cycle is extended to the next cycle by inserting a
wait state (T_w) and ADS is not asserted in the next cycle.
LOCK
I/O BUS LOCK prevents bus masters from gaining control of the L-Bus during
O.D. ^{Read/Modify/Write (RMW) cycles. The processor or any bus agent may assert}
LOCK.
At the start of a RMW operation, the processor examines the LOCK pin. If the pin is
already asserted, the processor waits until it is not asserted. If the pin is not asserted,
the processor asserts LOCK during the T_a cycle of the read transaction. The
processor deasserts LOCK in the T_a cycle of the write transaction. During the time
LOCK is asserted, a bus agent can perform a normal read or write but not a RMW
operation.
The processor also asserts LOCK during interrupt-acknowledge transactions.
Do not leave LOCK unconnected. It must be pulled high for the processor to function
properly.
I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state
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