IA6805E2_07 Datasheet, PDF (8/33 Pages) InnovASIC, Inc – Microprocessor Unit

IA6805E2
Microprocessor Unit
Registers:
As of Production Version 00
29 August 2007
The following paragraphs describe the registers contained in the MPU. Figure 6 shows the
programming model and Figure 7 shows the interrupt stacking order.
7
7
12
PCH
87
12
6
0000001
0
A
ACCUMULATOR
0
X
INDEX REGISTER
PCL
0
PROGRAM COUNTER
0
SP
STACK POINTER
4
CC
0
H I N Z C CONDITION CODE REGISTER
CARRY/BORROW
ZERO
NEGATIVE
INTERRUPT MASK
HALF CARRY
Figure 6. Programming Model
NOTE: Since the stack pointer decrements during pushes, the PCL is stacked first,
followed by PCH, etc. Pulling from the stack is in the reverse order.
INCREASING MEMORY
ADDRESSES
1
R
E
T
U
R
N0
UNSTACK
11
CONDITION CODE
REGISTER
ACCUMULATOR
INDEX REGISTER
00
PCH
PCL
STACK
I
N
T
E
R
R
DECREASING MEMORY
ADDRESSES
U
P
T
Figure 7. Interrupt Stacking Order
Copyright © 2007
©
IA211081401-03
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