IA6805E2_07 Datasheet, PDF (3/33 Pages) InnovASIC, Inc – Microprocessor Unit

IA6805E2
Microprocessor Unit
As of Production Version 00
29 August 2007
Description
The IA6805E2 (CMOS) Microprocessor Unit (MPU) is a low cost, low power MPU. It features a
CPU, on-chip RAM, parallel I/O compatibility with pins programmable as input or output. The
following paragraphs will further describe this system block diagram and design in more detail.
TIMER
PRESCALER
TIMER/
COUNTER
TIMER CONTROL
OSC1 OSC2
OSCILLATOR
PA0
PA0
PA1
PA2
PORT
A
PA3
I/O PA4
LINES _PA5
PA6
PA7
PORT
A
REG
DATA
DIR
REG
PB0
PB1
PB2
PORT
B
PB3
I/O PB4
LINES _PB5
PB6
PB7
PORT
B
REG
DATA
DIR
REG
ACCUMULATOR
8
A
INDEX
REGISTER
8
X
CONDITION
CODE
5 ^REGISTER CC
STACK
POINTER
6
SP
PROGRAM
COUNTER
5 ^HIGH PCH
PROGRAM
COUNTER
8 ^LOW PCL
CPU
RESET_N
LI
IRQ_N
CPU
CONTROL
ALU
112x8
RAM
MUX
BUS
DRIVE
B0
B1
B2
MULTIPLEXED
B3
ADDRESS
B4
DATA
BUS
B5
B6
B7
ADDRESS
DRIVE
A8
A9
A10
ADDRESS
BUS
A11
A12
BUS
CONTROL
AS
DS
RW_N
ADDRESS STROBE
DATA STROBE
READ/WRITE
Figure 1. System Block Diagram
Copyright © 2007
©
IA211081401-03
Page 3 of 33
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