IA6805E2_07 Datasheet, PDF (14/33 Pages) InnovASIC, Inc – Microprocessor Unit

IA6805E2
Microprocessor Unit
As of Production Version 00
29 August 2007
Stop Modes:
The stop instruction places the MPU in low power consumption mode. The stop instruction
disables clocking of most internal registers. Timer control register bits 6 and 7 (TCR6 and
TCR7) are altered to remove any pending timer interrupt requests and to disable any further
timer interrupts. The DS and AS output lines go “low” and the RW_n line goes “high”. The
multiplexed address/data bus goes to the data input state. The high order address lines
remain at the address of the next instruction. External interrupts are enabled by clearing the
I bit in the condition code register. All other registers, memory, and I/O remain unaltered.
Only an external interrupt or reset will bring the MPU out of the stop mode. Figure 11
shows a flowchart of the stop function.
STOP
TCR BIT 7 <= 0
TCR BIT 6 <= 1
CLEAR I BIT
N
N
EXTERNAL
INTERRUPT?
Y
RESET?
Y
FETCH EXTERNAL
INTERRUPT
OR RESET VECTOR
Figure 11. STOP Function Flowchart
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IA211081401-03
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