IA6805E2_07 Datasheet, PDF (11/33 Pages) InnovASIC, Inc – Microprocessor Unit

IA6805E2
Microprocessor Unit
As of Production Version 00
29 August 2007
RESET
I_CC <= 1
SP <= $007F
DDRs <= 0
CLR IRQ_N LOGIC
TIMER <= $FF
PRESCALER <= $7F
TCR <= $7f
PUT 1FFE,1FFF ON
ADDRESS BUS
SET
I BIT
?
CLEAR
IRQ_N
EDGE
Y
?
N
TCR6=0
AND
Y
TCR7=1?
N
Y
RESET_N
PIN = LOW
IN
RESET
?
N RESET_N
PIN = LOW
LOAD PC
FROM
1FFE/1FFF
FETCH
INSTRUCTION
IS FETCHED
INSTRUCTION
Y
AN SWI?
N
EXECUTE ALL
INSTRUCTION
CYCLES
CLEAR
IRQ_N
REQUEST
LATCH
IRQ_N
STACK
PC, X, A, CC
I <= 1
TIMER
LOAD PC FROM:
SWI: 1FFC/1FFD
IRQ_N: 1FFA/1FFB
TIMER: 1FF8/1FF9
TIMER WAIT:1FF6/
1FF7
PC+1=>PC
SWI
Figure 8. Reset and Interrupt Processing Flowchart
Copyright © 2007
©
IA211081401-03
Page 11 of 33
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