IA6805E2_07 Datasheet, PDF (26/33 Pages) InnovASIC, Inc – Microprocessor Unit

IA6805E2
Microprocessor Unit
Bus Timing
V_SS=0V, T_A=T_L to T_H (Figure 19)
As of Production Version 00
29 August 2007
Num
Parameters
1 Cycle Time
2 Pulse Width, DS Low
3 Pulse Width, DS High
4 Clock Transition
8 RW_n
9 Non-Muxed Address Hold
11 RW_n Delay From DS Fall
16 Non-Muxed Address Delay From AS Rise
17 MPU Read Data Setup
18 Read Data Hold
19 MPU Data Delay, Write
21 Write Data Hold
23 Muxed Address Delay From AS Rise
24 Muxed Address Valid to AS Fall
25 Muxed Address Hold
26 Delay DS Fall to AS Rise
27 Pulse Width, AS High
28 Delay, AS Fall to DS Rise
V_DD = 5.0V ±10%
f_OSC = 5MHz
1 TTL, 100pF Load ^Unit
Min
Max
1000
DC
ns
587
-
ns
403
-
ns
-
4
ns
9
-
ns
97
-
ns
-
40
ns
-
11
ns
18
-
ns
0
ns
-
0
ns
204
-
ns
-
26
ns
185
-
ns
103
-
ns
190
-
ns
203
-
ns
185
-
ns
ADDRESS_STROBE
PORT_INPUT
PORT_OUTPUT
V_LOW = 0.8V, V_HIGH = V_DD – 2.0V, V_DD = 5.0V ±10%
T_A = T_L to T_H, C_L on Port = 50pF, f_OSC = 5MHz
*NOTE
t_PVASL
t_ASLPX
t_ASLPV
*Note: The address strobe of the first cycle of the next instruction.
Figure 14. I/O Port Timing
Copyright © 2007
©
IA211081401-03
Page 26 of 33
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