IA70C20 Datasheet, PDF (27/27 Pages) InnovASIC, Inc – 8-Bit Microcontroller

IA70C20
8-Bit Microcontroller
7. 70cX0 Errata
Data Sheet
August 19, 2008
When in MC mode, bus contents do not match cycle for cycle outside of qualified
data times. IE. When ALE or ENABLE_N are not active, we do not necessarily
match.
When in MC mode, our part does NOT assert RW_N when performing writes to
internal registers. OEM part does assert RW_N during internal writes, but not
consistently.
Stack addressing „underflow‟ or „under roll‟ behavior. Behavior is different
between our part vs. oem when an uneven number of „pop‟ operations are done
for a given number of „push‟ operations. If you „pop‟ below register file address
0x00 the OEM will stay at 0x00 for the first illegal pop, then go somewhere below
0x00. Given „n‟ illegal pop operations it will take „n-1‟ push operations to bring
stack pointer back to a valid number (0x00). The InnovASIC design will pop
down to 0x00 then stop. Any push operations after reaching 0x00 will result in
incrementing of stack address.
Register File addressing – when performing an instruction which manipulates two
register file locations such as decrement double on address 0x00 of register file.
OEM operates on first byte at 0x00, then decrements to 0xFF which is NOT a
valid register file location. Our part decrements to the top of real physical
memory 0x7F.
8. Revision History
The table below presents the sequence of revisions to document IA211030117.
Date
August 19,
2008
Revision
05
Description
Page(s)
Corrected control number and reformatted NA
some elements to meet publication
standards.
IA211030117-05
Page 27 of 27
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