IA70C20 Datasheet, PDF (20/27 Pages) InnovASIC, Inc – 8-Bit Microcontroller

IA70C20
8-Bit Microcontroller
Data Sheet
August 19, 2008
TMS7000 Family Instruction Overview (Continued)
Mnemonic
Opcode Bytes Cycles Status
Operation Description
Tc(C) C N Z I
INC A
B3
1
5
R R R x (Rd) + 1  (Rd)
B
C3
1
5
Increase the destination operand by 1
Rd
D3
2
7
INV A
B4
1
5
0 R R x NOT(Rd)  (Rd)
B
C4
1
5
1‟s complement the destination operand.
Rd
D4
2
7
JMP Ofst
D0
2
7
x x x x (PC) + offset  (PC)
The PC is modified by an offset to create
a new PC value.
(1)
xxxx
JC Ofst
JEQ Ofst
E3
2
5 (7)
E2
2
5 (7)
If conditions are met, then (PC) + offset
 (PC)
JHS Ofst
E3
2
5 (7)
If the needed conditions are met, the PC
JL Ofst
E7
2
5 (7)
is modified by the offset to form a new
JN Ofst
E1
2
5 (7)
PC value.
JNC Ofst
E7
2
5 (7)
JNE Ofst
E6
2
5 (7)
JNZ Ofst
E6
2
5 (7)
JP Ofst
E4
2
5 (7)
JPZ Ofst
E5
2
5 (7)
JZ Ofst
E2
2
5 (7)
LDA @Label
8A
3
11
0 R R x (XADDR)  (A)
@Label(B)
AA
3
13
Move the source operand to A.
*Rn
9A
2
10
LDSP
0D
1
5
x x x x (B)  (SP)
Load SP with register B‟s contents.
MOV A,B
C0
1
6
0 R R x (s)  (Rd)
A,Rd
D0
2
8
Replace the destination operand with the
B,A
62
1
5
source operand.
B,Rd
D1
2
7
Rs,A
12
2
8
Rs,B
32
2
8
Rs,Rd
42
3
10
%>iop,A
22
2
7
%>iop,B
52
2
7
%>iop,Rd
72
3
9
MOVD %>iop,Rp
88
4
15
0 R R x (s)  (Rd)
%>iop(B),Rp
A8
4
17
Copy the source register pair to the
Rp,Rp
98
3
14
destination register pair.
MOVP A,Pd
82
2
10
0 R R x (s)  (Pd) or (Ps)  (d)
B,Pd
92
2
9
Copy the source operand into the
%>iop,Pd
A2
3
11
destination operand.
Ps,A
80
2
9
Ps,B
91
2
8
Note: Add two to cycle count if branch is taken
Legend:
0
Status bit set always to 0.
1
Status bit set always to 1
R
Status bit set to a 1 or a 0 depending on results of operation.
x
Status bit not affected.
b
Bit ( ) affected.
Ofst Offset
IA211030117-05
Page 20 of 27
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