IA70C20 Datasheet, PDF (19/27 Pages) InnovASIC, Inc – 8-Bit Microcontroller

IA70C20
8-Bit Microcontroller
Data Sheet
August 19, 2008
TMS7000 Family Instruction Overview (Continued)
Mnemonic
Opcode Bytes Cycles Status
Tc(C) C N Z I
CMP B,A
6D
1
5
RRRx
Rn,A
1D
2
8
Rn,B
3D
2
8
Rn,Rn
4D
3
10
%iop,A
2D
2
7
%iop,B
5D
2
7
%iop,Rn
7D
3
9
CMPA @Label
8D
3
12
RRRx
@Label(B)
AD
3
14
*Rn
9D
2
11
DAC B,A
6E
1
7
RRRx
Rs,A
1E
2
10
Rs,B
3E
2
10
Rs,Rd
4E
3
12
%>iop,A
2E
2
9
%>iop,B
5E
2
9
%>iop,Rd
7E
3
11
DEC A
B2
1
5
RRRx
B
C2
1
5
Rd
D2
2
7
DECD A
BB
1
9
RRRx
B
CB
1
9
Rp
DB
2
11
DINT
06
1
5
0000
(1)
DJNZ A,Ofst
B,Ofst
Rd,Ofst
BA
1
CA
2
DA
2
7 (9)
7 (9)
9 (11)
xxxx
Operation Description
(Rn) – (s) computed but not stored
Set flags on the result of the source
operand subtracted from the destination
operand.
(A) – (XADDR) computed but not stored
Set flags on result of the source operand
subtracted from A.
(s) + (Rd) + (C)  (Rd) (BCD)
The source, destination, and the carry bit
are added, and the BCD sum is stored at
the destination address. Contents on the s
+ Rd operands initially need to be the
BCD.
(Rd) – 1  (Rd)
Decrement destination operand by 1.
(Rd) – 1  (Rp)
Decrement register pair by 1.C=0 on 0 –
FFFF transition
0  (global interrupt enable bit). Clear
the I bit.
(Rd) – 1  (Rd);
If (Rd) 0,
(PC) + offset  (PC)
DSB B,A
6F
1
7
R R R x (Rd) – (s) – 1 + (C)  (Rd) (BCD)
Rs,A
1F
2
10
The source of the operand is subtracted
Rs,B
3F
2
10
from the destination; this sum is then
Rs,Rd
4F
3
12
reduced by 1 and the carry bit is then
%>iop,A
2F
2
9
added to it. The result is stored as a BCD
%>iop,B
5F
2
9
number. Contents on the s + Rd operands
%>iop,Rd
7F
3
11
initially need to be BCD.
EINT
05
1
5
1 1 1 1 2  (global interrupt enable bit).
3 Set the I bit.
IDLE
01
1
6
x x x x (PC)  (PC) until interrupt
(PC) + 1  (PC) after return from
interrupt
Stops C execution until an interrupt.
Note: Add two to cycle count if branch is taken
Legend:
0
Status bit set always to 0.
1
Status bit set always to 1
R
Status bit set to a 1 or a 0 depending on results of operation.
x
Status bit not affected.
b
Bit ( ) affected.
Ofst Offset
IA211030117-05
Page 19 of 27
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