PEB20550 Datasheet, PDF (94/407 Pages) Infineon Technologies AG – ICs for Communications

PEB 20550
PEF 20550
Operational Description
The actual position of the external upstream and downstream PCM-frames with respect
to the framing signal PFS can still be adjusted using the PCM-offset function of the
EPIC-1. The offset can then be programmed such that PFS marks any bit number of the
external frame.
Furthermore it is possible to select either the rising or falling PDC-clock edge for
transmitting and sampling the PCM-data.
Usually, the repetition rate of the applied framing pulse PFS is identical to the frame
period (125 µs). If this is the case, the loss of synchronism indication function can
be used to supervise the clock and framing signals for missing or additional clock cycles.
The EPIC-1 checks the PFS-period internally against the duration expected from the
programmed data rate. If, for example, double clock operation with 32 time slots per
frame is programmed, the EPIC-1 expects 512 clock periods within one PFS-period. The
synchronous state is reached after the EPIC-1 has detected two consecutive correct
frames. The synchronous state is lost if one bad clock cycle is found. The
synchronization status (gained or lost) can be read from an internal register and each
status change generates an interrupt.
3.5.2 Configurable Interface
The serial configurable interface (CFI) can be operated either in duplex modes or in a bi-
directional mode.
In duplex modes the EPIC-1 provides up to four ports consisting each of a data output
(DD#) and a data input (DU#) line. The output pins are called "Data Downstream" pins
and the input pins are called "Data Upstream" pins. These modes are especially suited
to realize a standard serial PCM-interface (PCM-highway) or to implement an IOM
(ISDN-Oriented Modular) interface. The IOM-interface generated by the EPIC-1 offers
all the functionality like C/I- and monitor channel handling required for operating all kinds
of IOM compatible layer-1 and codec devices.
In bi-directional mode the EPIC-1 provides eight bi-directional ports (SIP). Each time
slot at any of these ports can individually be programmed as input or output. This mode
is mainly intended to realize an SLD-interface (Serial Line Data). In case of an SLD-
interface the frame consists of eight time slots where the first four time slots serve as
outputs (downstream direction) and the last four serve as inputs (upstream direction).
The SLD-interface generated by the EPIC-1 offers signaling and feature control channel
handling.
Data is transmitted and received at normal TTL/CMOS-levels at the CFI. Tristate or
open-drain output drivers can be selected. In case of open-drain drivers, external pull-
up resistors are required. Unassigned output time slots may be switched to high
impedance or be programmed to transmit a defined idle value. The selection between
the states "high impedance" or "idle value" can be performed on a per time slot basis.
Semiconductor Group
94
01.96