PEB20550 Datasheet, PDF (338/407 Pages) Infineon Technologies AG – ICs for Communications

5.8.4 Power and Clock Supply Supervision/Chip Version
PEB 20550
PEF 20550
Application Hints
Power and Clock Supply Supervision
The + 5 V power supply line (V_DD) and the reference clock (RCL) are continuously
checked by the ELIC for spikes that may disturb the proper operation of the ELIC. If such
an inappropriate clocking or power failure occurs, data in the internal memories may be
lost, and a reinitialization of the ELIC is necessary. An Initialization Request status bit
(VNSR:IR) can be interrogated periodically by the µP to determine the current status of
the device.
In normal chip operation, the IR bit should never be set, not even after power on or when
the clock signals are switched on and off. The IR bit will only be set if spikes (< 10 ns)
are detected on the clock and power lines which may affect the data transfer on the ELIC
internal buses.
Semiconductor Group
338
01.96