PEB20550 Datasheet, PDF (280/407 Pages) Infineon Technologies AG – ICs for Communications

PEB 20550
PEF 20550
Application Hints
Data Upstream
– At the CFI interface the incoming data (data upstream) is written to the RAM starting
with DU0 at the beginning of:
time slot: 2 × n for CFI mode 0
time slot: 2 × n for CFI mode 1
time slot: 2 × n for CFI mode 2
Note: n is an integer number; the time slot number can’t exceed the max. number of TS.
The point of time to write the data to the RAM is RCL period 1 and 3 for the CFI interface
– At the PCM interface the data, that is to be transmitted on
TS 2 × n + 4 ... TS 2 × n + 5 (for PCM mode 0)
TS 4 × n + 8 ... TS 4 × n + 11 (for PCM mode 1)
TS 8 × n + 16 ... TS 8 × n + 23 (for PCM mode 2)
is read out of the RAM as soon as time slot:
2 × n (for PCM mode 0)
4 × n + 1 (for PCM mode 1)
8 × n + 3 (for PCM mode 2) is transmitted
Note: n is an integer number; the time slot number can’t exceed the max. number of TS.
The point of time to read the data from the RAM, is RCL period 0, 4, 7 for the PCM
interface
Due to internal delays, the RCL period at the beginning of time slot 2 × n + 1 (for PCM 0),
4 × n + 2 (for PCM mode1), 8 × n + 4 for PCM mode 2) is no valid write cycle.
The data is read out of the RAM in two steps:
PCM mode 0: in a block of 2 TS for TXD0 … 1 then for TXD2 … 3
PCM mode 1: in a block of 4 TS for TXD0 then for TXD2
PCM mode 2: in halfs of a 8 TS blocks for TXD0 (first half) then for TXD0
(second half)
Semiconductor Group
280
01.96