PEB20550 Datasheet, PDF (152/407 Pages) Infineon Technologies AG – ICs for Communications

PEB 20550
PEF 20550
Detailed Register Description
CTB2..0 Note that if a CFI time slot is selected as receive or transmit time slot of the
synchronous transfer, the 64-kBit/s bandwidth must be selected
(CT#2..CT#0 = 001).
CT#2
0
0
0
0
1
1
1
1
CT#1
0
0
1
1
0
0
1
1
CT#0
0
1
0
1
0
1
0
1
Bandwidth
not allowed
64 kBit/s
32 kBit/s
32 kBit/s
16 kBit/s
16 kBit/s
16 kBit/s
16 kBit/s
Transferred Bits
–
bits 7..0
bits 3..0
bits 7..4
bits 1..0
bits 3..2
bits 5..4
bits 7..6
4.6.23 MF-Channel Active Indication Register (MFAIR)
Access in demultiplexed µP-interface mode:
Access in multiplexed µP-interface mode:
Reset value: 00_H
read/write
read/write
address: 0A_H
address: 14_H
bit 7
0
bit 0
SO
SAD5 SAD4 SAD3 SAD2 SAD1 SAD0
This register is only used in IOM-2 applications (active handshake protocol) in order to
identify active monitor channels when the "Search for active monitor channels"
command (CMDR:MFSO) has been executed.
SO
SAD5..0
MF Channel Search On.
0…the search is completed.
1…the EPIC-1 is still busy looking for an active channel.
Subscriber Address 5..0; after an ISTA:MAC-interrupt these bits point to the
port and time slot where an active channel has been found. The coding is
identical to MFSAR:SAD5..SAD0.
Semiconductor Group
152
01.96