PEB20550 Datasheet, PDF (215/407 Pages) Infineon Technologies AG – ICs for Communications

PEB 20550
PEF 20550
Application Hints
Internal Reference
Clock (RCL)
CMD2 : COC
DCL
M
U
X * _x2
* Only CFI
Modes 0 and 3
CMD2 : FC2 ... 0
FSC
FC Modes 0-7
CFI Frame Sync.
C
F
I CFI Data Rate
ELIC ^R
CFI Mode
2
÷2
1
CMD1: CSP1, 0
0
3
CFI Mode
2
M
CRCL U
÷1.5
X
÷2
1
0
÷2
3
÷4
Bit Shift
CTAR
CBSR : CDS2...0
Bit Shift
POFU
POFD
PCSR
PMOD : PCR
M
U
X
÷2
PCM Frame Sync.
PCM Data Rate
PDC
PFS
P
C
M
ITS08045
Figure 66
ELIC^® Clock Sources for the CFI and PCM Interfaces if CMD1:CSS = 0
If DCL and FSC are selected as clock and framing signal source (CMD1:CSS = 1),
the CFI reference clock CRCL is obtained out of the DCL input signal after division by 1,
1.5 or 2 according to the prescaler selection (CMD1:CSP1 … 0). The CFI frame
structure is synchronized by the FSC input signal. Note that although the frequency and
phase of DCL and FSC may be chosen almost independently with respect to the
frequency and phase of PDC and PFS, the CFI clock source must still be synchronous
to the PCM interface clock source i.e. the two clock sources must always be derived from
one master clock. This mode must be selected if it is impossible to derive the required
CFI data rate from the PCM clock source. An overview of the different possibilities to
generate the PCM and CFI data and clock rates for CMD1:CSS = 1 is given in figure 67.
Semiconductor Group
215
01.96