ICE3GS03LJG Datasheet, PDF (9/25 Pages) Infineon Technologies AG – Of f-Line SMPS Current Mode Controller wi th integrated 500V Startup Cell

F3 PWM controller
ICE3GS03LJG
Functional Description
to the line variations. The current waveform slope will
change with the line variation, which controls the duty
cycle.
The external R_Sense allows an individual adjustment of
the maximum source current of the external power
MOSFET.
To improve the Current Mode during light load
V_OSC
max.
Duty Cycle
conditions the amplified current ramp of the PWM-OP
is superimposed on a voltage ramp, which is built by
the switch T2, the voltage source V1 and a resistor R1
(see Figure 6). Every time the oscillator shuts down for
Voltage Ramp
t
maximum duty cycle limitation the switch T2 is closed
by V_OSC. When the oscillator triggers the Gate Driver,
T2 is opened so that the voltage ramp can start.
In case of light load the amplified current ramp is too
small to ensure a stable regulation. In that case the
0.67V
FB
Voltage Ramp is a well defined signal for the
comparison with the FB-signal. The duty cycle is then
controlled by the slope of the Voltage Ramp.
Gate Driver
t
By means of the time delay circuit which is triggered by
the inverted V_OSC signal, the Gate Driver is switched-off
until it reaches approximately 156ns delay time (see
156ns time delay
Figure 7). It allows the duty cycle to be reduced
continuously till 0% by decreasing V_FB below that
threshold.
t
Soft-Start Comparator
PWM Comparator
FB
Oscillator
C8
PWM-Latch
V_OSC
time delay
circuit (156ns)
Gate Driver
T₂
C₁
0.67V
10k
X3.3
R₁
V_{1 PWM OP}
Voltage Ramp
Figure 6 Improved Current Mode
Figure 7 Light Load Conditions
3.3.1 PWM-OP
The input of the PWM-OP is applied over the internal
leading edge blanking to the external sense resistor
R_Sense connected to pin CS. R_Sense converts the source
current into a sense voltage. The sense voltage is
amplified with a gain of 3.3 by PWM OP. The output of
the PWM-OP is connected to the voltage source V₁.
The voltage ramp with the superimposed amplified
current signal is fed into the positive inputs of the PWM-
Comparator C8 and the Soft-Start-Comparator (see
Figure 6).
3.3.2 PWM-Comparator
The PWM-Comparator compares the sensed current
signal of the external power MOSFET with the
feedback signal V_FB (see Figure 8). V_FB is created by an
external optocoupler or external transistor in
combination with the internal pull-up resistor R_FB and
provides the load information of the feedback circuitry.
When the amplified current signal of the external power
MOSFET exceeds the signal V_FB the PWM-
Comparator switches off the Gate Driver.
Version 2.0
9
1 Nov 2010