ICE3GS03LJG Datasheet, PDF (15/25 Pages) Infineon Technologies AG – Of f-Line SMPS Current Mode Controller wi th integrated 500V Startup Cell

F3 PWM controller
ICE3GS03LJG
Functional Description
3.7.2.1 Entering Active Burst Mode
The FB signal is kept monitoring by the comparator C4.
During normal operation, the internal blanking time
counter is reset to 0. When FB signal falls below 1.23V,
it starts to count. When the counter reach 20ms and FB
signal is still below 1.23V, the system enters the Active
Burst Mode. This time window prevents a sudden
entering into the Active Burst Mode due to large load
jumps.
V_FB
4.2V
3.5V
3.0V
1.23V
Entering
Active Burst
Mode
Leaving
Active Burst
Mode
After entering Active Burst Mode, a burst flag is set and
the internal bias is switched off in order to reduce the _{Blanking Timer}
t
current consumption of the IC to approx. 450mA.
20ms Blanking Time
It needs the application to enforce the VCC voltage
above the Undervoltage Lockout level of 10.5V such
that the Startup Cell will not be switched on
accidentally. Or otherwise the power loss will increase
drastically. The minimum VCC level during Active Burst
Mode depends on the load condition and the
application. The lowest VCC level is reached at no load
condition.
V_CS
t
3.7.2.2 Working in Active Burst Mode
After entering the Active Burst Mode, the FB voltage
rises as V_OUT starts to decrease, which is due to the
inactive PWM section. The comparator C6a monitors
the FB signal. If the voltage level is larger than 3.5V, the
1.06V
0.25V
Current limit level
during Active Burst
Mode
internal circuit will be activated; the Internal Bias circuit
resumes and starts to provide switching pulse. In
V_VCC
t
Active Burst Mode the gate G10 is released and the
current limit is reduced to 0.25V. In one hand, it can
reduce the conduction loss and the other hand, it can
reduce the audible noise. If the load at V_OUT is still kept
unchanged, the FB signal will drop to 3.0V. At this level
the C6b deactivates the internal circuit again by
switching off the internal Bias. The gate G11 is active
10.5V
again as the burst flag is set after entering Active Burst
Mode. In Active Burst Mode, the FB voltage is changing
I_VCC
t
like a saw tooth between 3.0V and 3.5V (see Figure
24).
2.5mA
3.7.2.3 Leaving Active Burst Mode
The FB voltage will increase immediately if there is a
high load jump. This is observed by the comparator C4. _450uA
As the current limit is app. 25% during Active Burst
Mode, a certain load jump is needed so that the FB
signal can exceed 4.2V. At that time the comparator C4
V_OUT
t
resets the Active Burst Mode control which in turn
blocks the comparator C12 by the gate G10. The
maximum current can then be resumed to stabilize
V_OUT.
Version 2.0
t
Figure 24 Signals in Active Burst Mode
15
1 Nov 2010