ICE3GS03LJG Datasheet, PDF (12/25 Pages) Infineon Technologies AG – Of f-Line SMPS Current Mode Controller wi th integrated 500V Startup Cell

F3 PWM controller
ICE3GS03LJG
Functional Description
Start block. Then the switching frequency is varied in
range of 130kHz ± 5.2kHz at period of 4ms.
3.5.2
PWM-Latch FF
The output of the oscillator block provides continuous
pulse to the PWM-Latch which turns on/off the external
power MOSFET. After the PWM-Latch is set, it is reset
by the PWM comparator, the Soft Start comparator or
the Current -Limit comparator. When it is in reset mode,
the output of the gate driver is shut down immediately.
Thus the leading switch on spike is minimized.
Furthermore the driver circuit is designed to eliminate
cross conduction of the output stage.
During power up, when VCC is below the undervoltage
lockout threshold V_VCCoff, the output of the Gate Driver
is set to low in order to disable power transfer to the
secondary side.
3.6 Current Limiting
3.5.3
Gate Driver
VCC
PW M -Latch
1
Gate Driver
Gate
PWM Latch Latched Off
FF1
Mode
Spike
Blanking
190ns
Current Limiting
1.66V
C11
Propagation-Delay
Compensation
OPP
V_csth
C10
Leading
Edge
PWM-OP
Blanking
220ns
&
G10
C12
0.25V
Figure 15 Gate Driver
The driver-stage is optimized to minimize EMI and to
provide high circuit efficiency. This is done by reducing
the switch on slope when exceeding the external power
MOSFET threshold. This is achieved by a slope control
of the rising edge at the gate driver’s output (see Figure
16).
ca. t = 130ns
5V
t
Figure 16 Gate Rising Slope
Active Burst
Mode
10k
1pF
D1
CS
Figure 17 Current Limiting Block
There is a cycle by cycle peak current limiting operation
realized by the Current-Limit comparator C10. The
source current of the external power MOSFET is
sensed via an external sense resistor R_Sense. By means
of R_Sense the source current is transformed to a sense
voltage V_Sense which is fed into the pin CS. If the voltage
V_Sense exceeds the internal threshold voltage V_csth, the
comparator C10 immediately turns off the gate drive by
resetting the PWM Latch FF1.
A Propagation Delay Compensation is added to
support the immediate shut down of the external power
MOSFET with very short propagation delay. Thus the
influence of the AC input voltage on the maximum
output power can be reduced to minimal.
In order to prevent the current limit from distortions
caused by leading edge spikes, a Leading Edge
Version 2.0
12
1 Nov 2010