ICE3AR10080CJZ Datasheet, PDF (9/33 Pages) Infineon Technologies AG – Off-Line SMPS Current Mode Controller with integrated 800V CoolMOS® and Startup cell (brownout & CCM) in DIP-7

CoolSET^®-F3R80
ICE3AR10080CJZ
Functional Description
Latched Off Mode. This is done usually by re-cycling
the AC line.
When Active Burst Mode is entered, the internal Bias is
switched off most of the time but the Voltage Reference
is kept alive in order to reduce the current consumption
below 620mA.
3.3
Improved Current Mode
Soft-Start Comparator
FBB
C8
0.6V
PWM-Latch
RQ
Driver
SQ
In case the amplified current sense signal exceeds the
FBB signal the on-time t_on of the driver is finished by
resetting the PWM-Latch (Figure 5).
The primary current is sensed by the external series
resistor R_Sense inserted in the source of the integrated
CoolMOS^®. By means of Current Mode regulation, the
secondary output voltage is insensitive to the line
variations. The current waveform slope will change with
the line variation, which controls the duty cycle.
The external R_Sense allows an individual adjustment of
the maximum source current of the integrated
CoolMOS^®.
To improve the Current Mode during light load
conditions the amplified current ramp of the PWM-OP
is superimposed on a voltage ramp, which is built by
the switch T2, the voltage source V1 and a resistor R1
(see Figure 6). Every time the oscillator shuts down for
maximum duty cycle limitation the switch T2 is closed
by V_OSC. When the oscillator triggers the Gate Driver,
T2 is opened so that the voltage ramp can start.
PWM OP
x3.25
CS
Improved
Current Mode
Soft-Start Comparator
PWM Comparator
FBB
Oscillator
C8
PWM-Latch
Figure 4 Current Mode
Current Mode means the duty cycle is controlled by the
slope of the primary current. This is done by comparing
the FBB signal with the amplified current sense signal.
Amplified Current Signal
FBB
V_OSC
T₂
time delay
circuit (156ns)
Gate Driver
0.6V
10k
R₁
X3.25
V_{1 PWM OP}
0.6V
Driver
t_on
Figure 5 Pulse Width Modulation
Voltage Ramp
t
Figure 6 Improved Current Mode
In case of light load the amplified current ramp is too
small to ensure a stable regulation. In that case the
Voltage Ramp is a well defined signal for the
comparison with the FBB-signal. The duty cycle is then
t
controlled by the slope of the Voltage Ramp.
By means of the time delay circuit which is triggered by
the inverted V_OSC signal, the Gate Driver is switched-off
until it reaches approximately 156ns delay time (Figure
Version 2.0
9
11 Jan 2012