ICE3AR10080CJZ Datasheet, PDF (16/33 Pages) Infineon Technologies AG – Off-Line SMPS Current Mode Controller with integrated 800V CoolMOS® and Startup cell (brownout & CCM) in DIP-7

CoolSET^®-F3R80
ICE3AR10080CJZ
Functional Description
During IC first startup, the Ref_good signal is logic low
when Vcc<8V. The low Ref_good signal will reset the
Burst Mode level Detection latch. When the Burst Mode
Level Detection latch is low and IC is in OFF state, the
FBB resistor is isolated from the FBB pin and a current
source I_sel (3.5mA) is turned on instead.
From Vcc=8V to Vcc on threshold(17V), the FBB pin
will start to charge to a voltage level associated with
R_sel resistor. When Vcc reaches Vcc on threshold, the
FBB voltage is sensed. The burst mode thresholds are
then chosen according to the FBB voltage level. The
Burst Mode Level Detection latch is then set to high.
Once the detection latch is set high, any change of the
FBB level will not change the threshold level. When
Vcc reaches Vcc on threshold, a timer of 2ms is started.
After the 2ms ends, the I_sel is turned off while the FBB
resistor is connected to FBB pin (Figure 24).
3.7.1.3 Working in Active Burst Mode
After entering the Active Burst Mode, the FBB voltage
rises as VOUT starts to decrease, which is due to the
inactive PWM section. The comparator C6a monitors
the FBB signal. If the voltage level is larger than 3.5V,
the internal circuit will be activated; the Internal Bias
circuit resumes and starts to provide switching pulse. In
Active Burst Mode the gate G6 is released and the
current limit is reduced to Vcsth_burst (Figure 2 and
23). In one hand, it can reduce the conduction loss and
the other hand, it can reduce the audible noise. If the
load at VOUT is still kept unchanged, the FBB signal
will drop to 3.2V. At this level the C6b deactivates the
internal circuit again by switching off the Internal Bias.
The gate G11 is active again as the burst flag is set
after entering Active Burst Mode. In Active Burst Mode,
the FBB voltage is changing like a saw tooth between
3.2V and 3.5V (Figure 25).
V_dd
Isel
UVLO
Ref_good
S
2µs
R
delay
Burst mode
detection latch
S2
Rfb
S1
FBB
Vcsth_burst
Selection
Compare
Vref1
V_{FB_burst}
Logic
logic
Vref2
Control unit
3.7.1.4 Leaving Active Burst Mode
The FBB voltage will increase immediately if there is a
high load jump. This is observed by the comparator
C13 (Figure 23). Since the current limit is reduced to
0.21V~0.34V during active burst mode, it needs a
certain load jump to rise the FBB signal to exceed 4.0V.
At that time the comparator C5 resets the Active Burst
Mode control which in turn blocks the comparator C12
by the gate G6. The maximum current can then be
resumed to stabilize V_OUT.
Figure 24 Burst mode detect and adjust
3.7.1.2 Entering Active Burst Mode
The FBB signal is kept monitoring by the comparator
C5 (Figure 23). During normal operation, the internal
blanking time counter is reset to 0. When FBB signal
falls below V_{FB_burst}, it starts to count. When the counter
reaches 20ms and FBB signal is still below V_{FB_burst}, the
system enters the Active Burst Mode. This time window
prevents a sudden entering into the Active Burst Mode
due to large load jumps.
After entering Active Burst Mode, a burst flag is set and
the internal bias is switched off in order to reduce the
current consumption of the IC to about 620mA.
It needs the application to enforce the VCC voltage
above the Undervoltage Lockout level of 10.5V such
that the Startup Cell will not be switched on
accidentally. Or otherwise the power loss will increase
drastically. The minimum VCC level during Active Burst
Mode depends on the load condition and the
application. The lowest VCC level is reached at no load
condition.
Version 2.0
16
11 Jan 2012