ICE3AR10080CJZ Datasheet, PDF (13/33 Pages) Infineon Technologies AG – Off-Line SMPS Current Mode Controller with integrated 800V CoolMOS® and Startup cell (brownout & CCM) in DIP-7

CoolSET^®-F3R80
ICE3AR10080CJZ
Functional Description
3.5.3
Gate Driver
VCC
PWM-Latch
1
50
Gate
CoolMOS^®
3.6 Current Limiting
PWM Latch
FF1
Propagation-Delay
Compensation
Current Limiting
PWM-OP
&
G6
V_csth
C10
LEB
220ns ^S4
LEB
180ns
C12
V_{CSth_burst}
Gate Driver
Figure 16 Gate Driver
The driver-stage is optimized to minimize EMI and to
provide high circuit efficiency. This is done by reducing
the switch on slope when exceeding the integrated
CoolMOS^® threshold. This is achieved by a slope
control of the rising edge at the driver’s output (Figure
17) and adding a 50W gate turn on resistor (Figure 16).
Thus the leading switch on spike is minimized.
(internal)
V_Gate
typ. t = 160ns
4.6V
t
Figure 17 Gate Rising Slope
Furthermore the driver circuit is designed to eliminate
cross conduction of the output stage.
During power up, when VCC is below the undervoltage
lockout threshold V_VCCoff, the output of the Gate Driver
is set to low in order to disable power transfer to the
secondary side.
Active Burst
Mode
V_{FB_burst}
C5
Propagation-Delay
Compensation-Burst
or
G8
10k
1pF
D1
FBB
CS
Figure 18 Current Limiting Block
There is a cycle by cycle peak current limiting operation
realized by the Current-Limit comparator C10. The
source current of the integrated CoolMOS^® is sensed
via an external sense resistor R_Sense. By means of
R_Sense the source current is transformed to a sense
voltage V_Sense which is fed into the pin CS. If the voltage
V_Sense exceeds the internal threshold voltage V_csth, the
comparator C10 immediately turns off the gate drive by
resetting the PWM Latch FF1.
A Propagation Delay Compensation is added to
support the immediate shut down of the integrated
CoolMOS^® with very short propagation delay. Thus the
influence of the AC input voltage on the maximum
output power can be reduced to minimal. This
compensation applies to both the peak load and burst
mode.
In order to prevent the current limit from distortions
caused by leading edge spikes, a Leading Edge
Blanking (LEB) is integrated in the current sense path
for the comparators C10, C12 and the PWM-OP.
The output of comparator C12 is activated by the Gate
G6 if Active Burst Mode is entered. When it is activated,
the current limiting is reduced to V_{csth_burst}. This voltage
level determines the maximum power level in Active
Burst Mode.
Version 2.0
13
11 Jan 2012