ICB2FL02G Datasheet, PDF (7/55 Pages) Infineon Technologies AG – Smart Ballast Control IC for Fluorescent Lamp Ballasts

2^nd Generation FL-Controller for FL-Ballasts
LSGD (Low-side Gate drive, Pin 2)
The Gate of the low-side MOSFET in a half-
bridge inverter topology is controlled by this pin.
There is an active L-level during UVLO (under
voltage lockout) and a limitation of the max H-
level at 11.0 V during normal operation. In order
to turn-on the MOSFET softly (with a reduced
di_DRAIN/dt); the Gate voltage rises within 220ns
typically from L-level to H-level. The fall time of
the Gate voltage is less than 50ns in order to
turn off quickly. This measure produces
different switching speeds during turn-on and
turn-off as it is usually achieved with a diode
parallel to a resistor in the Gate drive loop. It is
recommended to use a resistor of typically 10Ω
between drive pin and Gate in order to avoid
oscillations and in order to shift the power
dissipation of discharging the Gate capacitance
into this resistor. The dead time between LSGD
signal and HSGD signal is self adapting
between 1.05µs and 2.0µs.
Vcc (Supply voltage, Pin 3)
This pin provides the power supply of the
ground related section of the IC. There is a
turn-on threshold at 14.1V and an UVLO
threshold at 10.6V. Upper supply voltage level
is 17.5V. There is an internal zener diode
clamping V_CC at 16.3V (at I_VCC=2mA typically).
The maximum zener current is internally limited
to 5mA. For higher current levels an external
zener diode is required. Current consumption
during UVLO and during fault mode is less than
170µA. A ceramic capacitor close to the supply
and GND pin is required in order to act as a
low-impedance power source for Gate drive
and logic signal currents. In order to use a
skipped preheating after short interruptions of
mains supply it is necessary to feed the start-up
current (160µA) from the bus voltage. Note: for
external V_CC supply see notes in flowchart
chapter 3.3.
GND (Ground, Pin 4)
This pin is connected to ground and represents
the ground level of the IC for supply voltage,
Gate drive and sense signals.
PFCGD (PFC Gate drive, Pin 5)
The Gate of the MOSFET in the PFC
preconverter designed in boost topology is
controlled by this pin. There is an active L-level
during UVLO and a limitation of the max H-level
at 11.0 V during normal operation. In order to
turn-on the MOSFET softly (with a reduced
di_DRAIN/dt), the Gate drive voltage rises within
220ns from L-level to H-level.
The fall time of the Gate voltage is less than
50ns in order to turn off quickly.
A resistor of typically 10Ω between drive pin
and Gate in order to avoid oscillations and in
order to shift the power dissipation of
discharging the Gate capacitance into this
resistor is recommended.
The PFC section of the IC controls a boost
converter as a PFC preconverter in
discontinuous conduction mode (DCM).
Typically the control starts with Gate drive
pulses with a fixed on-time of typically 4.0µs at
V_ACIN = 230V increasing up to 22.7µs and with
an off-time of 47µs. As soon as sufficient zero
current detector (ZCD) signals are available,
the operation mode changes from a fixed
frequent operation to an operation with variable
frequency. The PFC works in a critical
conduction mode operation (CritCM) when
rated and / or medium load conditions are
present. That means triangular shaped currents
in the boost converter choke without gaps and
variable operating frequency. During low load
(detected by an internal compensator) we get
an operation with discontinuous conduction
mode (DCM) that means triangular shaped
currents in the boost converter choke with gaps
when reaching the zero current level and
variable operating frequency in order to avoid
steps in the consumed line current.
PFCCS (PFC current sense, Pin 6)
The voltage drop across a shunt resistor
located between Source of the PFC MOSFET
and GND is sensed with this pin. If the level
exceeds a threshold of 1.0 V for longer than
200ns the PFC Gate drive is turned off as long
as the zero current detector (ZCD) enables a
new cycle. If there is no ZCD signal available
within 52µs after turn-off of the PFC Gate drive,
a new cycle is initiated from an internal start-up
timer.
PFCZCD (PFC zero current detector, Pin 7)
This pin senses the point of time when the
current through boost inductor becomes zero
during off-time of the PFC MOSFET in order to
initiate a new cycle.
The moment of interest appears when the
voltage of the separate ZCD winding changes
from positive to negative level which represents
a voltage of zero at the inductor windings and
therefore the end of current flow from lower
input voltage level to higher output voltage
level. There is a threshold with hysteresis, for
increasing level 1.5V, for decreasing level 0.5V,
which detects the change of inductor voltage.
Preliminary Datasheet
Page 7 of 55
ICB2FL02G
V1.2