ICB2FL02G Datasheet, PDF (14/55 Pages) Infineon Technologies AG – Smart Ballast Control IC for Fluorescent Lamp Ballasts

2^nd Generation FL-Controller for FL-Ballasts
Functional Description
In case of V_CC exceeds the 10.6 V level and stays below 14.1 V (Start up Hysteresis – phase 2 Figure
5), the IC checks whether the lamps are assembled by detecting a current across the filaments.
The low side filaments are checked from a source current of typical I_RES3 = - 21.3 µA out of PIN 12
RES
(Figure 5 I_RES). This current produces a voltage drop of V_RES < 1.6 V (filament is ok) at the low side
filament sense resistor (R 36 in Figure 3), connected to GND (via low side filament). An open low side
filament is detected (see chapter 2.3.2), when the voltage at the RES PIN exceeds the V_RES > 1.6V
threshold (Figure 5 V_RES).
The high side filaments are checked by a current of I_LVS > 12 µA typically via resistors R41, R42, R43
and R44 (Figure 3) into the LVS1 PIN 13 (for a single lamp operation) and LVS2 PIN 14 for a multi
lamp operation. Note: in case of a single lamp operation, the unused LVS PIN has to be disabled via
connection to GND. An open high side filament is detected (see 2.3.3) when there is no sink current
into the LVS PIN. This causes a higher source current out of the RES PIN (typical 42.6 µA / 35.4 µA)
in order to exceed V_RES > 1.6 V. In case of defect filaments, the IC keeps monitoring until there is an
adequate current from the RES or the LVS PIN present (e.g. in case of removal a defect lamp).
When V_CC exceeds the 14.1 V threshold - by the end of the start up hysteresis in phase 2 Figure 5 -
the IC waits for 130µs and senses the bus voltage. When the rated bus voltage is in the corridor of
12.5% < V_BUSrated < 105% the IC powers up the system and enters phase 3 (Figure 5 V_BUSrated > 95 %
sensing) when not, the IC initiates an UVLO when the chip supply voltage is below V_CC < 10.6 V. As
soon as the condition for a power up is fulfilled, the IC starts the inverter gate operation with an
internal fixed Start Up frequency of 135 kHz. The PFC gate drive starts with a delay of app. 300µs.
Now, the bus voltage will be checked for a rated level above 95 % for a duration of 80 ms (phase 3
Figure 5). When leaving phase 3, the IC enters the Soft Start phase and shifts the frequency from the
internal fixed Start Up frequency of 135 kHz down to the set Preheating frequency e.g. f_RFPH = 100
kHz.
Preliminary Datasheet
Page 14 of 55
ICB2FL02G
V1.2