XC228X_08 Datasheet, PDF (64/125 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance

XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Functional Description
3.10
A/D Converters
For analog signal measurement, up to two 10-bit A/D converters (ADC0, ADC1) with
16 + 8 multiplexed input channels and a sample and hold circuit have been integrated
on-chip. They use the successive approximation method. The sample time (to charge
the capacitors) and the conversion time are programmable so that they can be adjusted
to the external circuit. The A/D converters can also operate in 8-bit conversion mode,
further reducing the conversion time.
Several independent conversion result registers, selectable interrupt requests, and
highly flexible conversion sequences provide a high degree of programmability to meet
the application requirements. Both modules can be synchronized to allow parallel
sampling of two input channels.
For applications that require more analog input channels, external analog multiplexers
can be controlled automatically.
For applications that require fewer analog input channels, the remaining channel inputs
can be used as digital input port pins.
The A/D converters of the XC228x support two types of request sources which can be
triggered by several internal and external events.
• Parallel requests are activated at the same time and then executed in a predefined
sequence.
• Queued requests are executed in a user-defined sequence.
In addition, the conversion of a specific channel can be inserted into a running sequence
without disturbing that sequence. All requests are arbitrated according to the priority
level assigned to them.
Data reduction features, such as limit checking or result accumulation, reduce the
number of required CPU access operations allowing the precise evaluation of
analoginputs (high conversion rate) even at a low CPU speed.
The Peripheral Event Controller (PEC) can be used to control the A/D converters or to
automatically store conversion results to a table in memory for later evaluation, without
requiring the overhead of entering and exiting interrupt routines for each data transfer.
Each A/D converter contains eight result registers which can be concatenated to build a
result FIFO. Wait-for-read mode can be enabled for each result register to prevent the
loss of conversion data.
In order to decouple analog inputs from digital noise and to avoid input trigger noise,
those pins used for analog input can be disconnected from the digital input stages under
software control. This can be selected for each pin separately with registers P5_DIDIS
and P15_DIDIS (Port x Digital Input Disable).
The Auto-Power-Down feature of the A/D converters minimizes the power consumption
when no conversion is in progress.
Data Sheet
62
V2.1, 2008-08