XC228X_08 Datasheet, PDF (40/125 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance

XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Functional Description
3.1
Memory Subsystem and Organization
The memory space of the XC228x is configured in the von Neumann architecture. In this
architecture all internal and external resources, including code memory, data memory,
registers and I/O ports, are organized in the same linear address space.
Table 5
XC228x Memory Map
Address Area
Start Loc. End Loc. Area Size¹⁾ Notes
IMB register space
FF’FF00_H FF’FFFF_H 256 Bytes –
Reserved (Access trap) F0’0000_H FF’FEFF_H <1 Mbyte
Minus IMB registers
Reserved for EPSRAM E9’0000_H EF’FFFF_H 448 Kbytes Mirrors EPSRAM
Emulated PSRAM
E8’0000_H E8’FFFF_H 64 Kbytes Flash timing
Reserved for PSRAM E1’0000_H E7’FFFF_H 448 Kbytes Mirrors PSRAM
Program SRAM
E0’0000_H E0’FFFF_H 64 Kbytes Maximum speed
Reserved for pr. mem. CC’0000_H DF’FFFF_H <1.25 Mbytes –
Program Flash 2
C8’0000_H CB’FFFF_H 256 Kbytes –
Program Flash 1
C4’0000_H C7’FFFF_H 256 Kbytes –
Program Flash 0
C0’0000_H C3’FFFF_H 256 Kbytes ²⁾
External memory area 40’0000_H BF’FFFF_H 8 Mbytes
–
Available Ext. IO area³⁾ 20’5800_H 3F’FFFF_H < 2 Mbytes Minus USIC/CAN
USIC registers
20’4000_H 20’57FF_H 6 Kbytes
Accessed via EBC
MultiCAN registers
20’0000_H 20’3FFF_H 16 Kbytes Accessed via EBC
External memory area 01’0000_H 1F’FFFF_H < 2 Mbytes Minus segment 0
SFR area
00’FE00_H 00’FFFF_H 0.5 Kbyte
–
Dual-Port RAM
00’F600_H 00’FDFF_H 2 Kbytes
–
Reserved for DPRAM 00’F200_H 00’F5FF_H 1 Kbyte
–
ESFR area
00’F000_H 00’F1FF_H 0.5 Kbyte
–
XSFR area
00’E000_H 00’EFFF_H 4 Kbytes
–
Data SRAM
00’A000_H 00’DFFF_H 16 Kbytes –
Reserved for DSRAM 00’8000_H 00’9FFF_H 8 Kbytes
–
External memory area 00’0000_H 00’7FFF_H 32 Kbytes –
1) The areas marked with “<” are slightly smaller than indicated. See column “Notes”.
2) The uppermost 4-Kbyte sector of the first Flash segment is reserved for internal use (C0’F000_H to C0’FFFF_H).
3) Several pipeline optimizations are not active within the external IO area. This is necessary to control external
peripherals properly.
Data Sheet
38
V2.1, 2008-08