XC228X_08 Datasheet, PDF (51/125 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance

XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Functional Description
The XC228x includes an excellent mechanism to identify and process exceptions or
error conditions that arise during run-time, the so-called ‘Hardware Traps’. A hardware
trap causes an immediate non-maskable system reaction similar to a standard interrupt
service (branching to a dedicated vector table location). The occurrence of a hardware
trap is also indicated by a single bit in the trap flag register (TFR). Unless another higher-
priority trap service is in progress, a hardware trap will interrupt any ongoing program
execution. In turn, hardware trap services can normally not be interrupted by standard
or PEC interrupts.
Table 7 shows all possible exceptions or error conditions that can arise during runtime:
Table 7
Trap Summary
Exception Condition
Trap
Flag
Trap
Vector
Vector Trap Trap
Location¹⁾ Number Priority
Reset Functions
–
RESET
xx’0000_H 00_H
III
Class A Hardware Traps:
• System Request 0
SR0
SR0TRAP xx’0008_H 02_H
II
• Stack Overflow
STKOF STOTRAP xx’0010_H 04_H
II
• Stack Underflow
STKUF STUTRAP xx’0018_H 06_H
II
• Software Break
SOFTBRK SBRKTRAP xx’0020_H 08_H
II
Class B Hardware Traps:
• System Request 1
• Undefined Opcode
• Memory Access Error
• Protected Instruction
Fault
SR1
UNDOPC
ACER
PRTFLT
BTRAP
BTRAP
BTRAP
BTRAP
xx’0028_H 0A_H
I
xx’0028_H 0A_H
I
xx’0028_H 0A_H
I
xx’0028_H 0A_H
I
• Illegal Word Operand ILLOPA
Access
BTRAP
xx’0028_H 0A_H
I
Reserved
–
–
[2C_H - 3C_H] [0B_H - –
0F_H]
Software Traps:
–
–
Any
Any
Current
• TRAP Instruction
[xx’0000_H - [00_H -
xx’01FC_H] 7F_H]
in steps of
CPU
Priority
4_H
1) Register VECSEG defines the segment where the vector table is located to.
Bitfield VECSC in register CPUCON1 defines the distance between two adjacent vectors. This table
represents the default setting, with a distance of 4 (two words) between two vectors.
Data Sheet
49
V2.1, 2008-08