TLE4926C-HTNE6747 Datasheet, PDF (6/27 Pages) Infineon Technologies AG – Dynamic Differential Hall Effect Sensor

TLE4926C-HTN E6747
Trigger rules for offset update in running mode
As already mentioned, at either a positive or negative comparator edge the offset
may be updated. At this time, several circuit conditions are checked. The following
rules apply:
After a modification of the PGA setting the update capability is disabled. With the 3^rd
following comparator edge the update capability is enabled again.
After an offset update the update capability is disabled. With the 2^nd following
comparator edge the update capability is enabled again.
At any offset update the circuit checks if there has been a larger signal value than
that which is stored in the maximum register. In this case, the larger value will be
taken. The same (with opposite sign) is true for minimum values.
If a valid minimum or a valid maximum has been found and none of the above rules
is against it, a calibration may occur. This must not be the first calibration after the
initial calibration.
Any calibration may occur only at the correct comparator edge. This means that a
negative signal shift due to offset correction may occur only during the negative going
signal slope. The same is true for positive signal shift and the rising signal slope.
Watchdog operation
If for a certain time (2^20 clock pulses – 0.7 s) there is no switching at the output the
watchdog will start a new observation period. It is responsible for a new initialization
by issuing a system reset. So a new selfcalibration (successive approximation of
offset) is started and the PGA and GainDac are reseted (PGA=0, GainDac=100000
binary). During the selfcalibration the output is held to the old value, afterwards it is
switched according to the edge-detection.
The second check that is implemented is the PGA decrement: if no max or min is
found during 16 output- switching events the PGA is decremented by 1. No other
actions are performed if such a situation is detected.
Digital main-comparator
The digital main-comparator receives the output of the three threshold comparators
hypcomp_low, main_comp and hypcomp_high. This inputs are used in an
asynchronous way, so that no clock-delay is introduced.
The function of the digital main-comparator is to implement a hidden hysteresis; that
means, that the ouput switches accordingly to the main_comp threshold and the
upper and lower hysteresis limits are used to lock the output. In this way no
hysteresis is visible in the switching behavior and we have a high noise rejection.
Summary
The IC monitors the positive and negative peak values of the signal to adjust its
offset properly. For large deviations the actual offset correction value is calculated as
accurate as possible, for smaller deviations also a slow calibration mode by only
incrementing and decrementing or by not changing the offset value can be entered.
The device is monitored by a watchdog, which starts a new initialization if there is no
input signal.
Data Sheet
Page 6 of 27