TLE4926C-HTNE6747 Datasheet, PDF (4/27 Pages) Infineon Technologies AG – Dynamic Differential Hall Effect Sensor

TLE4926C-HTN E6747
B0H. This procedure ensures a sufficient resolution for each signal amplitude. After
doing the 6 bit A/D conversion running at system clock speed (1.455MHz), the values
are put into a simple decimation filter, which sums up 8 consecutive values and, by
truncating the least significant bit, delivers an 8 bit output signal at 1/8 system speed
(182kHz). The rest of the digital calibration process now refers to this 8 bit data (Min-
Max finding, offset calculation). The tracking converter as well as the PGA is
protected against overflow or underflow, so no wrap-around or undefined condition
can occurs. Instead the signal is clipped to a maximum or minimum value.
Finding the minimum and maximum values
During operation a dedicated logic block looks for the smallest numerical input value.
If the signal is falling, this block permanently stores new input values. If the signal is
larger than the stored value, the stored value remains memorized. If, after a minimum
value, the signal increases for a certain amount (digital noise constant) this
memorized value is called a minimum and propagated to another register (minimum
register). The same procedure (with opposite sign) applies to maximum values. The
digital noise constant has a value 30H with one exception: If the PGA is in maximum
amplification the digital noise constant is 48H. The noise constant is referred to the 8
bit Gain- Dac value. Each newly identified maximum starts another search for a new
minimum. Each newly identified minimum starts another search for a new maximum.
In this way alternating new minimum and maximum values can be identified. This
ensures, that “all time high” or –low values do not remain in memory. Instead, only
recent minimum and maximum values are obtainable.
Valid and invalid min/max values
After initialization, new calibration and PGA-changes the circuit starts a new search
for minimum and maximum values. Assuming the process starts at a rising signal
slope, then the initial point may become to a minimum since it is the lowest observed
value so far. This occurrence is memorized, but the minimum is called an invalid
minimum. The same can occur if the search starts at a falling edge for a maximum. A
minimum is called a valid minimum if it is preceded by any (valid or invalid)
maximum. The same is true for maximum values. Any minimum or maximum value is
discarded immediately, if there is a new initialization, new calibration or a PGA-
change.
Startup of the device
After power on or an internal reset a new calibration procedure is started. First, the
external comparator output is locked. Second, the offset-DAC is set in that way, that
it compensates the incoming signal. This is done by a successive approximation
search. For a steady state input signal the offset DAC therefore gets the value of this
input signal and the digital inputs are the digital representation of this value. For a
varying signal the approximation search ends up in a value which is somewhere near
the input signal during the duration of the successive approximation search. This is
the initial calibration value. Of course the remaining offset value may still be quite
large. Then the minimum and maximum search is started. After having found the first
minimum or maximum the output switches according to the definition (low output
Data Sheet
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