TC1912 Datasheet, PDF (56/68 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

PRELIMINARY
Timing for Demultiplexed Access Signals¹⁾
(Operating Conditions apply; C_L = 50 pF)
Parameter
ALE low from EBUCLK
ALE high from EBUCLK
A(23:0) output valid from EBUCLK
A(23:0) output hold from EBUCLK
CS(6:0) low from EBUCLK
CS(6:0) high from EBUCLK
MR/W low from EBUCLK
MR/W high from EBUCLK
RMW low from EBUCLK
RMW high from EBUCLK
RD low from EBUCLK
RD high from EBUCLK
RD/WR low from EBUCLK
RD/WR high from EBUCLK
CMDELAY input setup to EBUCLK
CMDELAY hold from EBUCLK
WAIT input setup to EBUCLK
WAIT hold from EBUCLK
BC(3:0) low from EBUCLK
BC(3:0) high from EBUCLK
AD(31:0) output valid from EBUCLK
AD(31:0) output hold from EBUCLK
AD(31:0) input setup to EBUCLK
AD(31:0) input hold from EBUCLK
TC1912
Symbol
Limits
min. max.
t₁ CC −
8.0
t₂ CC 2.0 −
t₃ CC −
8.0
t₄ CC 2.0 −
t₅ CC −
8.0
t₆ CC 2.0 −
t₇ CC −
8.0
t₈ CC 2.0 −
t₉ CC −
8.0
t₁₀ CC 1.0
−
t₁₁ CC −
8.0
t₁₂ CC 0.0
−
t₁₃ CC −
8.0
t₁₄ CC 2.0
t₁₅ SR 4.0
−
t₁₆ SR 3.0
−
t₁₇ SR 4.0
−
t₁₈ SR 3.0 −
t₁₉ CC −
8.0
t₂₀ CC 2.0 −
t₂₁ CC −
8.0
t₂₂ CC 0.0 −
t₂₃ SR 4.0 −
t₂₄ SR 4.0 −
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1) _{It is user responsibility to program an appropriate whole number of clock cycles to generate the correct phase}
length according to the particular asynchronous memory/peripheral device specification.
Data Sheet
52
V 1.0, 2003-10