TC1912 Datasheet, PDF (18/68 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1912
PRELIMINARY
On-chip Code Memories
Local Memory Bus Memory (LMBRAM):
Address range of the 64 KByte Local Memory Bus Memory:
• C000 0000_H - C000 FFFF_H (in segment 12 for cached operation)
• E800 0000_H - E800 FFFF_H (in segment 14 for non-cached operation)
PMU Scratch-Pad SRAM (CSRAM):
The Program Memory Unit (PMU) memory consists of 24-KByte Code Scratchpad RAM
(CSRAM) and 8-KByte Instruction Cache (ICACHE).
Address range of the CSRAM:
• D400 0000_H - D400 5FFF_H
On-chip Data Memories
DMU Scratch-Pad SRAM (DSRAM):
The Data Memory Unit (DMU) memory consists of 24-KByte Data Scratchpad RAM
(DSRAM) and 8-KByte Data Cache (DCACHE).
Address range of the DSRAM:
• D000 0000_H - D000 5FFF_H
FPI-Bus Data Memory (FPIDRAM):
The FPI-Bus Data Memory (FPIDRAM) is a 16-KByte static RAM located on the FPI-
Bus. It contains two parts: FPIDRAM0 and FPIDRAM1. One half of it (FPIDRAM1) can
be used for standby power operation.
Address range of the FPI Data Memory:
• 9FFF 8000_H - 9FFF BFFF_H (in segment 9 for cached operation)
• BFFF 8000_H - BFFF BFFF_H (in segment 11 for non-cached operation)
Data Sheet
14
V 1.0, 2003-10