TC1912 Datasheet, PDF (19/68 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1912
PRELIMINARY
System Control Unit (SCU)
The System Control Unit of the TC1912 basically handles all system control tasks. All
these system functions are tightly coupled and therefore they are handled physically by
one unit, the SCU. The system tasks of the SCU are:
• Clock Generation and Control
• Reset control
• Power Management control and wake-up
• Watchdog timer
• Device identification
• Standby SRAM control
• External interrupt capability (8 sources)
System timer (STM)
The System Timer is designed for global system timing applications requiring both high
precision and long range. It is used by the CPU for software operating system issues.
Features:
• Free-running 56-bit counter
• All 56 bits can be read synchronously
• Different 32-bit portions of the 56-bit counter can be read synchronously
• Driven by clock, f _STM (normally identical with the system clock).
• Counting begins at power-on reset
• Continuous operation is not affected by any reset condition except power-on reset
External Bus Interface (EBU_LMB)
EBU_LMB is connected to the Local Memory Bus (LMB) of the TC1912 and also to the
FPI Bus. EBU_LMB is always a slave on the LMB and a master/slave on the FPI bus.
Any LMB masters thus can access external memories or devices through EBU_LMB.
Currently the maximum length of the bursts are according to the size of program and
data cache lines, i.e. 8 x 32-bit words. Single transfers (non-burst) are supported for 8-
bit, 16-bit and 32-bit wide access.
Data Sheet
15
V 1.0, 2003-10