TC1912 Datasheet, PDF (27/68 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1912
PRELIMINARY
Inter-IC Interface (IIC)
IIC supports a certain protocol to allow devices to communicate directly with each other
via two wires. One line is responsible for clock transfer and synchronization (SCL), the
other is responsible for the data transfer (SDA).
The on-chip IIC Bus module connects the platform buses to other external controllers
and/or peripherals via the two-line serial IIC interface. The IIC Bus module provides
communication at data rates of up to 400 kBit/s and features 7-bit addressing as well as
10-bit addressing. This module is fully compatible to the IIC bus protocol.
The module can operate in three different modes:
Master mode, where the IIC controls the bus transactions and provides the clock signal.
Slave mode, where an external master controls the bus transactions and provides the
clock signal.
Multimaster mode, where several masters can be connected to the bus, i.e. the IIC can
be master or slave.
The on-chip IIC bus module allows efficient communication via the common IIC bus. The
module unloads the CPU of low level tasks like:
• (De)Serialization of bus data.
• Generation of start and stop conditions.
• Monitoring the bus lines in slave mode.
• Evaluation of the device address in slave mode.
• Bus access arbitration in multimaster mode.
IIC Features:
• Extended buffer allows up to 4 send/receive data bytes to be stored.
• Selectable baud rate generation.
• Support of standard 100 kBaud and extended 400 kBaud data rates.
• Operation in 7-bit addressing mode or 10-bit addressing mode.
• Flexible control via interrupt service routines or by polling.
Data Sheet
23
V 1.0, 2003-10