TC1912 Datasheet, PDF (23/68 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1912
PRELIMINARY
On-Chip Debug System (OCDS)
The TC1912 architecture is supporting OCDS Level 1. This means access to FPI Bus
and the whole FPI address space via the JTAG interface pins.
On-Chip Peripheral Units
The TC1912 offers several on-chip peripheral units such as serial controllers, timer units,
and Codec module. Within the TC1912 all these peripheral units are connected to the
TriCore CPU/system via the FPI (Flexible Peripheral Interconnect) Bus. Several IO lines
on the TC1912 ports are reserved for these peripheral units to communicate with the
external world.
Peripheral Units of the TC1912:
• Three Asynchronous/Synchronous Serial Channels with baudrate generator, parity,
framing and overrun error detection, IrDA mode, FIFO buffers.
• One High Speed Synchronous Serial Channels with programmable data length and
shift direction
• TwinCAN Module with two interconnected CAN nodes for high efficiency data
handling via FIFO buffering and gateway data transfer
• IIC module
• One multi-functional General Purpose Timer Units with three 32-bit timer/counter
• Dual channel Codec interface
• GPIO blocks
Table 2
Peripheral Modules
Module
Address Range
Asynchronous
Serial Channel 0
(ASC0)
F000 0A00_H -
F000 0AFF_H
I/O Lines
RDX0, TDX0
Asynchronous
Serial Channel 1
(ASC1)
F000 0B00_H -
F000 0BFF_H
RDX1, TDX1
Asynchronous
Serial Channel 2
(ASC2)
F000 0C00_H -
F000 0CFF_H
RDX2, TDX2
Synchronous Serial F000 0800_H -
Channel (SSC)
F000 08FF_H
SCLK, MRST,
MTSR
Interrupt Nodes
ASC0_TSRC
ASC0_RSRC
ASC0_ESRC
ASC0_TBSRC
ASC1_TSRC
ASC1_RSRC
ASC1_ESRC
ASC1_TBSRC
ASC2_TSRC
ASC2_RSRC
ASC2_ESRC
ASC2_TBSRC
SSC_TSRC
SSC_RSRC
SSC_ESRC
Data Sheet
19
V 1.0, 2003-10