XC2361B Datasheet, PDF (45/128 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance

XC2361B, XC2363B, XC2364B, XC2365B
XC2000 Family / Value Line
Functional Description
3.3
Central Processing Unit (CPU)
The core of the CPU consists of a 5-stage execution pipeline with a 2-stage instruction-
fetch pipeline, a 16-bit arithmetic and logic unit (ALU), a 32-bit/40-bit multiply and
accumulate unit (MAC), a register-file providing three register banks, and dedicated
SFRs. The ALU features a multiply-and-divide unit, a bit-mask generator, and a barrel
shifter.
CPU
Prefetch
Unit
Branch
Unit
FIFO
IDX0
IDX1
QX0
QX1
+/-
Multiply
Unit
+/-
MAH
MAC
PMU
CSP
IP
CPUCON1
CPUCON2
Return
Stack
IFU
VECSEG
TFR
Injection/
Exception
Handler
2-Stage
Prefetch
Pipeline
5-Stage
Pipeline
IPIP
QR0
QR1
+/-
MRW
MCW
MSW
MAL
DPP0
DPP1
DPP2
DPP3
SPSEG
SP
STKOV
STKUN
ADU
Division Unit
Multiply Unit
MDC
PSW
MDH
ZEROS
Bit-Mask-Gen.
Barrel-Shifter
+/-
MDL
ONES
ALU
CP
RR1155
RR114R415
R14
GGPPRRss
GPRs
RR11
RR00R1
R0
RF
Buffer
WB
DMU
Figure 5 CPU Block Diagram
PSRAM
Flash/ROM
DPRAM
R15
R14
GPRs
R1
R0
DSRAM
EBC
Peripherals
mca04917_x.vsd
Data Sheet
45
V1.2, 2010-04