XC2361B Datasheet, PDF (40/128 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance

XC2361B, XC2363B, XC2364B, XC2365B
XC2000 Family / Value Line
Functional Description
3.1
Memory Subsystem and Organization
The memory space of the XC236xB is configured in the von Neumann architecture. In
this architecture all internal and external resources, including code memory, data
memory, registers and I/O ports, are organized in the same linear address space.
Table 8
XC236xB Memory Map ¹⁾
Address Area
Start Loc. End Loc.
IMB register space
Reserved
Reserved for EPSRAM
Emulated PSRAM
FF’FF00_H
F0’0000_H
E8’4000_H
E8’0000_H
FF’FFFF_H
FF’FEFF_H
EF’FFFF_H
E8’3FFF_H
Reserved for PSRAM
PSRAM
E0’4000_H E7’FFFF_H
E0’0000_H E0’3FFF_H
Reserved for Flash
C5’0000_H
Flash 1
C4’0000_H
Flash 0
C0’0000_H
External memory area
External IO area⁴⁾
40’0000_H
21’0000_H
Reserved
20’BC00_H
USIC0–2 alternate regs. 20’B000_H
MultiCAN alternate regs. 20’8000_H
Reserved
20’5800_H
USIC0–2 registers
20’4000_H
Reserved
20’6800_H
MultiCAN registers
20’0000_H
External memory area 01’0000_H
SFR area
00’FE00_H
Dualport RAM (DPRAM) 00’F600_H
Reserved for DPRAM 00’F200_H
ESFR area
00’F000_H
XSFR area
00’E000_H
Data SRAM (DSRAM) 00’A000_H
DF’FFFF_H
C4’FFFF_H
C3’FFFF_H
BF’FFFF_H
3F’FFFF_H
20’FFFF_H
20’BBFF_H
20’AFFF_H
20’7FFF_H
20’57FF_H
20’7FFF_H
20’3FFF_H
1F’FFFF_H
00’FFFF_H
00’FDFF_H
00’F5FF_H
00’F1FF_H
00’EFFF_H
00’DFFF_H
Area Size²⁾
256 Bytes
< 1 Mbyte
496 Kbytes
up to
16 Kbytes
496 Kbytes
up to
16 Kbytes
1,728 Kbytes
64 Kbytes
256 Kbytes³⁾
8 Mbytes
1,984 Kbytes
17 Kbytes
3 Kbytes
12 Kbytes
10 Kbytes
6 Kbytes
6 Kbytes
16 Kbytes
1984 Kbytes
0.5 Kbytes
2 Kbytes
1 Kbytes
0.5 Kbytes
4 Kbytes
16 Kbytes
Notes
Minus IMB registers
Mirrors EPSRAM
With Flash timing
Mirrors PSRAM
Program SRAM
Minus res. seg.
Accessed via EBC
Accessed via EBC
Accessed via EBC
Accessed via EBC
Data Sheet
40
V1.2, 2010-04