XC2361B Datasheet, PDF (109/128 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance

XC2361B, XC2363B, XC2364B, XC2365B
XC2000 Family / Value Line
Electrical Parameters
Table 32 External Bus Timing for Upper Voltage Range (cont’d)
Parameter
Symbol
Values
Unit Note /
Min. Typ. Max.
Test Condition
Address output valid delay t₁₃ CC −
8
15
ns
for AD15 ... AD0 (MUX
mode)
Output valid delay for CS t₁₄ CC −
7
13
ns
Data output valid delay for t₁₅ CC −
8
15
ns
AD15 ... AD0 (write data,
MUX mode)
Data output valid delay for t₁₆ CC −
8
15
ns
D15 ... D0 (write data,
DEMUX mode)
Output hold time for RD, t₂₀ CC -2
6
8
ns
WR(L/H)
Output hold time for BHE, t₂₁ CC -2
6
ALE
10
ns
Address output hold time t₂₃ CC -3
6
8
ns
for AD15 ... AD0
Output hold time for CS t₂₄ CC -3
6
Data output hold time for t₂₅ CC -3
6
D15 ... D0 and AD15 ...
AD0
11
ns
8
ns
Input setup time for
t₃₀ SR 25
15
−
ns
READY, D15 ... D0, AD15
... AD0
Input hold time READY, t₃₁ SR 0
-7
−
ns
D15 ... D0, AD15 ... AD0¹⁾
1) Read data are latched with the same internal clock edge that triggers the address change and the rising edge
of RD. Address changes before the end of RD have no impact on (demultiplexed) read cycles. Read data can
change after the rising edge of RD.
Table 33 is valid under the following conditions: C_L= 20 pF; voltage_range= lower ;
voltage_range= lower
Data Sheet
109
V1.2, 2010-04