PEF2256HV2.2 Datasheet, PDF (391/518 Pages) Infineon Technologies AG – E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications

RBS(1:0)
BIM
XBS(1:0)
FALC^®56
PEF 2256 H/E
T1/J1 Registers
Receive Buffer Size
00 = Buffer size: 2 frames
01 = Buffer size: 1 frame
10 = Buffer size: 96 bits
11 = Bypass of receive elastic store
Bit Interleaved Mode
Only applicable if bit SIC2.SSC2 is cleared. If SIC2.SSC2 is set high,
the bit interleaved mode is automatically performed.
0 = Byte interleaved mode
1 = Bit interleaved mode
Transmit Buffer Size
00 = Bypass of transmit elastic store
01 = Buffer size: 1 frame
10 = Buffer size: 2 frames
11 = Buffer size: 96 bits
System Interface Control 2 (Read/Write)
Value after reset: 00_H
7
0
SIC2
FFS SSF CRB SSC2 SICS2 SICS1 SICS0
(3F)
FFS
Force Freeze Signaling
Setting this bit disables updating of the receive signaling buffer and
current signaling information is frozen. After resetting this bit and
receiving a complete superframe updating of the signaling buffer is
started again. The freeze signaling status can also be generated
automatically by detection of a loss-of-signal alarm or a loss of frame
alignment or a receive slip (only if external register access through
RSIG is enabled). This automatic freeze signaling function is logically
ored with this bit.
The current internal freeze signaling status is output on pin RP(A to
D) with selected pin function FREEZE (PC(4:1).RPC(2:0) = 110).
Additionally this status is also available in register SIS.SFS.
User’s Manual
391
Hardware Description
DS1.1, 2003-10-23