PEF2256HV2.2 Datasheet, PDF (213/518 Pages) Infineon Technologies AG – E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications

FALC^®56
PEF 2256 H/E
Signaling Controller Operating Modes
MODE.MDS(2:0)
FLAG
ADDR
CTRL
RAH1,2 RAL1,2
0 1 1 Non-Auto/16
2)
2)
0 1 0 Non-Auto/8
RAH1,2 X
2)
RAH1,2
1 0 1 Transparent 1
2)
1 0 0 Transparent 0
DATA
CRC
1)
RFIFO
RSIS
1)
RFIFO
RSIS
1)
RFIFO
RSIS
1)
RFIFO
RSIS
FLAG
Description of Symbols:
compared with register
stored in FIFO or register
In case of 8-bit address the
control field starts here
1) CRC is optionally stored in RFIFO of HDLC channel 1, 2 or 3 if
CCR2.RCRC = 1 (channel 1)
CCR3.RCRC2 = 1 (channel 2)
CCR4.RCRC3 = 1 (channel 3)
2) Address is optionally stored in RFIFO of HDLC channel 1, 2 or 3 if
CCR2.RADD = 1 (channel 1)
CCR3.RADD2 = 1 (channel 2)
CCR4.RADD3 = 1 (channel 3)
F0235
Figure 80 HDLC Receive Data Flow
User’s Manual
213
Hardware Description
DS1.1, 2003-10-23