PEF2256HV2.2 Datasheet, PDF (297/518 Pages) Infineon Technologies AG – E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications

FALC^®56
PEF 2256 H/E
E1 Registers
Time Slot Select 3 (Read/Write)
Value after reset: 00_H
7
0
TSS3
TSS34 TSS33 TSS32 TSS31 TSS30 (A5)
TS3(4:0)
Time Slot Selection Code - HDLC Channel 3
Defines the time slot used by HDLC channel 3.
00000 =No time slot selected
00001 =Time slot 1
...
11111 =Time slot 31
Note:Different HDLC channels must use different time slots.
Test Pattern Control Register 0 (Read/Write)
Value after reset: 00_H
7
TPC0
FRA
0
(A8)
FRA
Framed/Unframed Selection
0 = PRBS is generated/monitored unframed.
Framing information is overwritten by the generator.
1 = PRBS is generated/monitored framed.
Time slot 0 is not overwritten by the generator and not observed
by the monitor.
User’s Manual
297
Hardware Description
DS1.1, 2003-10-23