PEF2256HV2.2 Datasheet, PDF (332/518 Pages) Infineon Technologies AG – E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications

XDU2
RPF2
FALC^®56
PEF 2256 H/E
E1 Registers
Transmit Data Underrun - HDLC Channel 2
Transmitted frame was terminated with an abort sequence because
no data was available for transmission in XFIFO2 and no XME2 was
issued.
Note: Transmitter and XFIFO2 are reset and deactivated if this
condition occurs. They are reactivated not before this interrupt
status register has been read. Thus, XDU2 should not be
masked via register IMR4.
Receive Pool Full - HDLC Channel 2
32 bytes of a frame have arrived in the receive FIFO2. The frame is
not yet completely received.
Interrupt Status Register 5 (Read)
ISR5
7
0
XPR2 XPR3 RME3 RFS3 RDO3 ALLS3 XDU3 RPF3 (6D)
All bits are reset when ISR5 is read.
If bit GCR.VIS is set, interrupt statuses in ISR5 are flagged although they are masked
via register IMR5. However, these masked interrupt statuses neither generate a signal
on INT, nor are visible in register GIS.
XPR2
Transmit Pool Ready - HDLC Channel 2
A data block of up to 32 bytes can be written to the transmit FIFO2.
XPR2 enables the fastest access to XFIFO2. It has to be used for
transmission of long frames, back-to-back frames or frames with
shared flags.
XPR3
Transmit Pool Ready - HDLC Channel 3
A data block of up to 32 bytes can be written to the transmit FIFO3.
XPR3 enables the fastest access to XFIFO3. It has to be used for
transmission of long frames, back-to-back frames or frames with
shared flags.
User’s Manual
332
Hardware Description
DS1.1, 2003-10-23