PEF2256HV2.2 Datasheet, PDF (274/518 Pages) Infineon Technologies AG – E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications

FALC^®56
PEF 2256 H/E
E1 Registers
Errored Second Mask (Read/Write)
Value after reset: FF_H
7
0
ESM
LFA
FER CER
AIS
LOS CVE SLIP EBE
(47)
ESM
Errored Second Mask
This register functions as an additional mask register for the interrupt
status bit Errored Second (ISR3.ES). A "1" in a bit position of ESM
deactivates the related second interrupt.
Clock Mode Register 3 (Read/Write)
Value after reset: 00_H
7
CMR3
CFAX(3:0)
CFAR(3:0)
0
(48)
Table 62
CFAX(3:0)
7_H
4_H
DCO-R and DCO-X Corner Frequency Programing (E1)
DCO-X Corner
Frequency [Hz]
CFAR(3:0)
DCO-R Corner
Frequency [Hz]
0.2
7
0.2
2.0
4
2.0
Disable Error Counter (Write)
Value after reset: 00_H
7
0
DEC
DRBD
DCEC3 DCEC2 DCEC1 DEBC DCVC DFEC (60)
DRBD
DCEC3
DCEC2
DCEC1
Disable Receive Buffer Delay
This bit has to be set before reading the register RBD. It is reset
automatically if RBD has been read.
Disable CRC Error Counter 3
Disable CRC Error Counter 2
Disable CRC Error Counter
User’s Manual
274
Hardware Description
DS1.1, 2003-10-23