PEF2256HV2.2 Datasheet, PDF (264/518 Pages) Infineon Technologies AG – E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications

FALC^®56
PEF 2256 H/E
E1 Registers
Loop Code Register 2 (Read/Write)
Value after reset: 00_H
7
0
LCR2
LDC7
LDC0 (3C)
LDC(7:0)
Line Loop-Back Deactivate Code
If enabled by bit FMR3.XLD = 1 the LLB deactivate code
automatically repeats until the LLB generator is stopped. Transmit
data is overwritten by the LLB code. LDC0 is transmitted last. For
correct operations bit LCR1.XPRBS has to cleared.
If LCR2 is changed while the previous deactivate code has been
detected and is still received, bit RSP.LLBDD will stay active until the
incoming signal changes or a receiver reset is initiated
(CMDR.RRES = 1).
Loop Code Register 3 (Read/Write)
Value after reset: 00_H
7
0
LCR3
LAC7
LAC0 (3D)
LAC(7:0)
Line Loop-Back Activate Code
If enabled by bit FMR3.XLU = 1 the LLB activate code automatically
repeats until the LLB generator is stopped. Transmit data is
overwritten by the LLB code. LAC0 is transmitted last. For correct
operations bit LCR1.XPRBS has to cleared.
If LCR3 is changed while the previous activate code has been
detected and is still received, bit RSP.LLBAD will stay active until the
incoming signal changes or a receiver reset is initiated
(CMDR.RRES = 1).
User’s Manual
264
Hardware Description
DS1.1, 2003-10-23