HYS72D128020GR-8-A Datasheet, PDF (3/25 Pages) Infineon Technologies AG – 2.5 V 184-pin Registered DDR-I SDRAM Modules

HYS 72Dxx0xxGR-7/8-A
Registered DDR-I SDRAM-Modules
Pin Definitions and Functions
A0 - A11,A12
Address Inputs
V_DD
(A12 for 256Mb & 512Mb based modules)
Power (+ 2.5 V)
BA0, BA1
DQ0 - DQ63
CB0 - CB7
RAS
CAS
WE
Bank Selects
Data Input/Output
Check Bits (x72 organization only)
Row Address Strobe
Column Address Strobe
Read/Write Input
V_SS
V_DDQ
V_DDID
V_DDSPD
V_REF
SCL
Ground
I/O Driver power supply
VDD Indentification flag
EEPROM power supply
I/O reference supply
Serial bus clock
CKE0, CKE1
Clock Enable
SDA
Serial bus data line
DQS0 - DQS8
SDRAM low data strobes
SA0 - SA2
slave address select
CK0, CK0
Differential Clock Input
NC
no connect
DM0 - DM8
DQS9 - DQS17
SDRAM low data mask/
high data strobes
DU
don’t use
CS0 - CS1
Chip Selects
RESET
Reset pin (forces register
inputs low) *)
*) for detailed description of the Power Up and Power Management on DDR Registered DIMMs see the
Application Note at the end of this datasheet
Address Format
Density Organization
256 MB
512 MB
512 MB
1 GB
32M x 72
64M × 72
64M x 72
128M × 72
Memory
Banks
1
1
2
2
SDRAMs
32M x 8
64M × 4
32M x 8
64M × 4
# of
SDRAMs
9
18
18
36
# of row/bank/
columns bits
13/2/10
13/2/11
13/2/10
13/2/11
Refresh Period Interval
8k
64 ms 7.8 µs
8k
64 ms 7.8 µs
8k
64 ms 7.8 µs
8k
64 ms 7.8 µs
INFINEON Technologies
3
2002-05-08 (revision 1.0)