HYS72D128020GR-8-A Datasheet, PDF (10/25 Pages) Infineon Technologies AG – 2.5 V 184-pin Registered DDR-I SDRAM Modules

HYS 72Dxx0xxGR-7/8-A
Registered DDR-I SDRAM-Modules
Operating, Standby and Refresh Currents (PC1600)
Symbol
Parameter/Condition
256MB 512MB 512MB 1GB
x72
1bank
x72
1bank
x72
2bank
x72
2bank
Unit ^Notes
-8
-8
-8
-8
MAX MAX MAX MAX
5
Operating Current: one bank; active / precharge; tRC = tRC MIN; tCK =
IDD0 tCK MIN; DQ, DM, and DQS inputs changing once per clock cycle;
810
address and control inputs changing once every two clock cycles
1620 1305 2610 mA 1, 4
IDD1
Operating Current: one bank; active/read/precharge; Burst = 4;
Refer to the following page for detailed test conditions.
900
1800 1395 2790 mA 1, 3, 4
IDD2P
Precharge Power-Down Standby Current: all banks idle; power-down
mode; CKE <= VIL MAX; tCK = tCK MIN
135
270
270
540 mA 2, 4
Precharge Floating Standby Current: /CS >= VIH MIN, all banks idle;
IDD2F CKE >= VIH MIN; tCK = tCK MIN ,address and other control inputs
315
changing once per clock cycle, VIN = VREF for DQ, DQS and DM.
Precharge Quiet Standby Current: /CS >= VIH MIN, all banks idle;
IDD2Q CKE >= VIH MIN; tCK = tCK MIN ,address and other control inputs
315
stable at >= VIH MIN or <= VIL MAX; VIN = VREF for DQ, DQS and DM.
Active Power-Down Standby Current: one bank active; power-down
IDD3P mode; CKE <= VIL MAX; tCK = tCK MIN;VIN = VREF for DQ, DQS and 135
DM.
Active Standby Current: one bank active; active / precharge;CS >= VIH
IDD3N ^{MIN; CKE >= VIH MIN; tRC = tRAS MAX; tCK = tCK MIN; DQ, DM, and}
495
DQS inputs changing twice per clock cycle; address and control inputs
changing once per clock cycle
Operating Current: one bank active; Burst = 2; reads; continuous burst;
IDD4R
address and control inputs changing once per clock cycle; 50% of data
outputs changing on every clock edge; CL = 2 for DDR200, and
DDR266A, CL=3 for DDR333; tCK = tCK MIN; IOUT = 0mA
1350
Operating Current: one bank active; Burst = 2; writes; continuous burst;
IDD4W ^{address and control inputs changing once per clock cycle; 50% of data}
outputs changing on every clock edge; CL = 2 for DDR200, and
DDR266A, CL=3 for DDR333; tCK = tCK MIN
1170
IDD5
Auto-Refresh Current: tRC = tRFC MIN, distributed refresh
IDD6 Self-Refresh Current: CKE <= 0.2V; external clock on; tCK = tCK MIN
1620
27
IDD7
Operating Current: four bank; four bank interleaving with BL=4;
Refer to the following page for detailed test conditions.
2025
630
630
270
990
2700
2340
3240
54
4050
630
630
270
990
1845
1665
2115
54
2520
1260 mA 2, 4
1260 mA 2, 4
540 mA 2, 4
1980 mA 2, 4
3690 mA 1, 3, 4
3330 mA 1, 4
4230 mA 1, 4
108 mA 2, 4
5040 mA 1, 3, 4
1. The module IDD values are calculated from the component IDD datasheet values as:
n * IDDx[component] for single bank modules (n: number of components per module bank)
n * IDDx[component] + n * IDD3N[component] for two bank modules (n: number of components per module bank)
2. The module IDD values are calculated from the component IDD datasheet values as:
n * IDDx[component] for single bank modules (n: number of components per module bank)
2 * n * IDDx[component] for two bank modules (n: number of components per module bank)
3. DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions
4. DRAM component currents only: module IDD will be measured differently depending upon register and PLL operation currents
5. Test condition for maximum values: VDD = 2.7V ,Ta = 10°C
INFINEON Technologies
10
2002-05-08 (revision 1.0)