HYS72D128020GR-8-A Datasheet, PDF (13/25 Pages) Infineon Technologies AG – 2.5 V 184-pin Registered DDR-I SDRAM Modules

HYS 72Dxx0xxGR-7/8-A
Registered DDR-I SDRAM-Modules
Electrical Characteristics & AC Timing for DDR-I components
(for reference only)
(0 °C ≤ T_A ≤ 70 °C; V_DDQ = 2.5V ± 0.2V; V_DD = 2.5V ± 0.2V)
Symbol
Parameter
t_RFC
t_RCD
t_RP
t_RRD
t_WR
t_DAL
t_WTR
t_XSNR
t_XSRD
t_REFI
Auto-refresh to Active/Auto-refresh
command period
Active to Read or Write delay
Precharge command period
Active bank A to Active bank B command
Write recovery time
Auto precharge write recovery
+ precharge time
Internal write to read command delay
Exit self-refresh to non-read command
Exit self-refresh to read command
Average Periodic
Refresh Interval
256Mbit based
DDR266A
-7
Min Max
DDR200
-8
Min Max
75
80
20
20
20
20
15
15
15
15
(twr/tck) + (trp/tck)
1
1
75
80
200
200
7.8
7.8
Unit Notes
ns 1-4
ns 1-4
ns 1-4
ns 1-4
ns 1-4
t_CK 1-4,9
t_CK 1-4
ns 1-4
t_CK 1-4
µs 1-4, 8
1. Input slew rate >=1V/ns for DDR266 and = 1V/ns for DDR200.
2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross:
the input reference level for signals other than CK/CK, is V_REF. CK/CK slew rate are >= 1.0 V/ns.
3. Inputs are not recognized as valid until V_REF stabilizes.
4. The Output timing reference level, as measured at the timing reference point indicated in AC Character-
istics (Note 3) is V_TT.
5. t_HZ and t_LZ transitions occur in the same access time windows as valid data transitions. These parame-
ters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or
begins driving (LZ).
6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for
this parameter, but system performance (bus turnaround) degrades accordingly.
7. The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or
before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifi-
cations of the device. When no writes were previously in progress on the bus, DQS will be transitioning
from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning
from HIGH to LOW at this time, depending on t_DQSS.
8. A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
9. For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the
actual system clock cycle time.
10. These parameters guarantee device timing, but they are not necessarily tested on each device
11. Fast slew rate >= 1.0 V/ns , slow slew rate >= 0.5 V/ns and < 1V/ns for command/address and CK & CK
slew rate >1.0 V/ns, measured between VOH(ac) and VOL(ac)
INFINEON Technologies
13
2002-05-08 (revision 1.0)