HYS72D128020GR-8-A Datasheet, PDF (12/25 Pages) Infineon Technologies AG – 2.5 V 184-pin Registered DDR-I SDRAM Modules

HYS 72Dxx0xxGR-7/8-A
Registered DDR-I SDRAM-Modules
Electrical Characteristics & AC Timing for DDR-I components
(for reference only)
(0 °C ≤ T_A ≤ 70 °C; V_DDQ = 2.5V ± 0.2V; V_DD = 2.5V ± 0.2V)
Symbol
Parameter
t_AC
t_DQSCK
t_CH
t_CL
t_HP
t_CK
t_CK
t_DH
t_DS
t_IPW
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
CK low-level width
Clock Half Period
Clock cycle time
CL = 2.5
CL = 2.0
DQ and DM input hold time
DQ and DM input setup time
Control and Addr. input pulse width (each
input)
DDR266A
-7
Min Max
− 0.75 + 0.75
− 0.75 + 0.75
0.45 0.55
0.45 0.55
min (t_CL, t_CH)
7
12
7.5
12
0.5
0.5
DDR200
-8
Min
− 0.8
Max
+ 0.8
− 0.8 + 0.8
0.45 0.55
0.45 0.55
min (t_CL, t_CH)
8
12
10
12
0.6
0.6
2.2
2.5
t_DIPW DQ and DM input pulse width (each input)
1.75
2
t_HZ
t_LZ
t_DQSS
t_DQSQ
Data-out high-impedence time from CK/CK
Data-out low-impedence time from CK/CK
Write command to 1st DQS latching transition
DQS-DQ skew
(for DQS & associated DQ signals)
− 0.75
− 0.75
0.75
+ 0.75
+ 0.75
1.25
+ 0.5
− 0.8
− 0.8
0.75
+ 0.8
+ 0.8
1.25
+ 0.6
t_QHS
t_QH
t_DQSL,H
t_DSS
Data hold skew factor
Data Output hold time from DQS
DQS input low (high) pulse width (write cycle)
DQS falling edge to CK setup time (write
cycle)
t_HP-t_QHS
0.35
0.2
+ 0.75
t_HP-t_QHS
0.35
0.2
t_DSH
DQS falling edge hold time from CK (write
cycle)
0.2
0.2
+ 1.0
t_MRD
t_WPRES
t_WPST
t_WPRE
t_IS
Mode register set command cycle time
Write preamble setup time
Write postamble
Write preamble
Address and control
input setup time
fast slew rate
slow slew rate
14
0
0.40
0.25
0.9
1.0
t_IH
Address and control
input hold time
fast slew rate
0.9
slow slew rate
1.0
t_RPRE
t_RPST
t_RAS
t_RC
Read preamble
Read postamble
Active to Precharge command
Active to Active/Auto-refresh command period
0.9
0.40
45
65
0.60
1.1
0.60
120,000
16
0
0.40
0.25
1.1
1.1
1.1
1.1
0.9
0.40
50
70
0.60
1.1
0.60
120,000
Unit Notes
ns 1-4
ns 1-4
t_CK 1-4
t_CK 1-4
ns 1-4
ns 1-4
ns 1-4
ns 1-4
ns 1-4
ns 1, 10
ns
1-4,
11
ns 1-4, 5
ns 1-4, 5
t_CK 1-4
ns 1-4
ns 1-4
ns 1-4
t_CK 1-4
t_CK 1-4
t_CK 1-4
ns 1-4
ns 1-4, 7
t_CK 1-4, 6
t_CK 1-4
ns
ns _2-4,
ns ^10,11
ns
t_CK 1-4
t_CK 1-4
ns 1-4
ns 1-4
INFINEON Technologies
12
2002-05-08 (revision 1.0)